__projnav.log

总体演示程序DEMO_FPGA.rar

le "top_fpga_demo.bld"...

NGDBUILD done.


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Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\demo_fpga/_ngo -nt timestamp -uc
top_fpga.ucf -p xc2s100e-pq208-6 top_fpga_demo.ngc top_fpga_demo.ngd 

Reading NGO file 'E:/DEMO_FPGA/top_fpga_demo.ngc' ...
Reading module "mem_infor.ngo" ( "mem_infor.ngo" unchanged since last run )...
Loading design module "e:\demo_fpga\_ngo\mem_infor.ngo"...

Applying constraints in "top_fpga.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "top_fpga_demo.ngd" ...

Writing NGDBUILD log file "top_fpga_demo.bld"...

NGDBUILD done.




Started process "Map".

Using target part "2s100epq208-6".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    3
Logic Utilization:
  Total Number Slice Registers:     199 out of  2,400    8%
    Number used as Flip Flops:                    183
    Number used as Latches:                        16
  Number of 4 input LUTs:           349 out of  2,400   14%
Logic Distribution:
    Number of occupied Slices:                         257 out of  1,200   21%
    Number of Slices containing only related logic:    257 out of    257  100%
    Number of Slices containing unrelated logic:         0 out of    257    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          451 out of  2,400   18%
      Number used as logic:                       349
      Number used as a route-thru:                102
   Number of bonded IOBs:            18 out of    142   12%
      IOB Flip Flops:                               1
   Number of Block RAMs:              2 out of     10   20%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  37,062
Additional JTAG gate count for IOBs:  912
Peak Memory Usage:  100 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "top_fpga_demo_map.mrp" for details.




Started process "Place & Route".




Constraints file: top_fpga_demo.pcf.
Loading device for application Rf_Device from file '2s100e.nph' in environment
E:/Program/EDA/Xilinx.
   "top_fpga_demo" is an NCD, version 3.1, device xc2s100e, package pq208, speed
-6

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 85.000
Celsius)
Initializing voltage to 1.700 Volts. (default - Range: 1.700 to 1.900 Volts)


Device speed data version:  "PRODUCTION 1.18 2005-01-22".


Device Utilization Summary:

   Number of BLOCKRAMs                 2 out of 10     20%
   Number of GCLKs                     2 out of 4      50%
   Number of External GCLKIOBs         1 out of 4      25%
      Number of LOCed GCLKIOBs         1 out of 1     100%

   Number of External IOBs            18 out of 142    12%
      Number of LOCed IOBs            18 out of 18    100%

   Number of SLICEs                  257 out of 1200   21%


Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989e8c) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.23
Phase 3.23 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs 

Phase 6.8
....................
Phase 6.8 (Checksum:9fe7f9) REAL time: 3 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 3 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 3 secs 

Writing design to file top_fpga_demo.ncd


Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 3 secs 

Starting Router

Phase 1: 1725 unrouted;       REAL time: 4 secs 

Phase 2: 1566 unrouted;       REAL time: 10 secs 

Phase 3: 433 unrouted;       REAL time: 12 secs 

Phase 4: 0 unrouted;       REAL time: 13 secs 

Total REAL time to Router completion: 13 secs 
Total CPU time to Router completion: 12 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|               clk1k |      GCLKBUF1| No   |   67 |  0.283     |  0.542      |
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      GCLKBUF0| No   |   42 |  0.054     |  0.409      |
+---------------------+--------------+------+------+------------+-------------+
|         u4/u0/sclkb |         Local|      |    6 |  0.113     |  3.461      |
+---------------------+--------------+------+------+------------+-------------+
|         u4/u0/sclka |         Local|      |    5 |  2.683     |  3.435      |
+---------------------+--------------+------+------+------------+-------------+
|        u5/u0/_n0001 |         Local|      |    7 |  1.851     |  3.648      |
+---------------------+--------------+------+------+------------+-------------+
|        u4/u1/_n0001 |         Local|      |    6 |  2.507     |  3.631      |
+---------------------+--------------+------+------+------------+-------------+
|                clk1 |         Local|      |    6 |  0.120     |  3.388      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 14 secs 
Total CPU time to PAR completion: 13 secs 

Peak Memory Usage:  76 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file top_fpga_demo.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '2s100e.nph' in environment
E:/Program/EDA/Xilinx.
   "top_fpga_demo" is an NCD, version 3.1, device xc2s100e, package pq208, speed
-6

Analysis completed Fri Mar 25 05:06:43 2005
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 3 secs 







Started process "Generate Programming File".

WARNING:PhysDesignRules:372 - Gated clock. Clock net u5/u0/_n0001 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net u4/u1/_n0001 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/DEMO_FPGA/electronic_organ.vhd" in Library work.
Entity <electronic_organ> compiled.
Entity <electronic_organ> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <electronic_organ> (Architecture <Behavioral>).
WARNING:Xst:819 - "E:/DEMO_FPGA/electronic_organ.vhd" line 48: The following signals are missing in the process sensitivity list:
   button<3>, button<2>, button<1>, button<0>.
INFO:Xst:1304 - Contents of register <cnt> in unit <electronic_organ> never changes during circuit operation. The register is replaced by logic.
Entity <electronic_organ> analyzed. Unit <electronic_organ> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <electronic_organ>.
    Related source file is "E:/DEMO_FPGA/electronic_organ.vhd".
    Found 1-bit register for signal <tone>.
    Found 18-bit comparator greater for signal <$n0003> created at line 53.
    Found 18-bit comparator greater for signal <$n0010> created at line 53.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <electronic_organ> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 1
 1-bit register                    : 1
# Comparators                      : 2
 18-bit comparator greater         : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <electronic_organ> ...
Loading device for application Rf_Device from file '2s100e.nph' in environment E:/Program/EDA/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block electronic_organ, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100epq208-6 

 Number of Slices:                       6  out of   1200     0%  
 Number of Slice Flip Flops:             1  out of   2400     0%  
 Number of 4 input LUTs:                10  out of   2400     0%  
 Number of bonded IOBs:                  6  out of    146     4%