page_dclk.vhd

总体演示程序DEMO_FPGA.rar

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-- Company: 
-- Engineer:
--
-- Create Date:    01:08:34 03/25/05
-- Design Name:    
-- Module Name:    page1 - digital_clock
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity page1 is
    Port ( en : in std_logic_vector(4 downto 0);
           addr: in std_logic_vector(4 downto 0);            
           din : in std_logic_vector(7 downto 0);
           oh : in std_logic_vector(7 downto 0);
           om : in std_logic_vector(7 downto 0);
           os : in std_logic_vector(7 downto 0);
           dout : out std_logic_vector(7 downto 0));
end page1;

architecture digital_clock of page1 is

begin
process(en,din,addr,oh,om,os)
begin
   if en="10001" then
      case addr is
	 when "10011"=>
	             dout<="0011"&oh(7 downto 4);
	 when "10100"=>
	             dout<="0011"&oh(3 downto 0);

	 when "10110"=>
	             dout<="0011"&om(7 downto 4);
	 when "10111"=>
	             dout<="0011"&om(3 downto 0);

	 when "11001"=>
	             dout<="0011"&os(7 downto 4);
	 when "11010"=>
	             dout<="0011"&os(3 downto 0);
	 when others=>
	             dout<=din;
	 end case;
   end if;
end process;	 

end digital_clock;