button2.vhd

总体演示程序DEMO_FPGA.rar

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-- Company: 
-- Engineer:
--
-- Create Date:    22:39:20 03/24/05
-- Design Name:    
-- Module Name:    button2 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity button2 is
    Port ( clk : in std_logic;
           ibutton : in std_logic;
           obutton : out std_logic);
end button2;

architecture Behavioral of button2 is

type state is (st0,st1,st2,st3);
signal current_state : state;

begin
process(clk)
begin
   if rising_edge(clk) then
      case current_state is
	 when st0=>
	         obutton<='1';
		    current_state<=st1;

      when st1=>
	         obutton<='0';
		    current_state<=st2;

      when st2=>
	         if ibutton='1' then
		       current_state<=st0;
		    end if;

	 when st3=>
	         if ibutton='0' then 
		       current_state<=st1;
		    end if;
		    
      when others=>
	            current_state<=st0;
	 end case;                  
   end if;
end process;
end Behavioral;