demo2.vhd

总体演示程序DEMO_FPGA.rar

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--数码管显示
entity demo2 is
    Port (clk : in std_logic;
	       imode : in std_logic_vector(2 downto 0);
	       ibutton : in std_logic;
			 cs,cs1 : out std_logic;
			 led : out std_logic_vector(7 downto 0);
			 led_shift : out std_logic_vector(3 downto 0));
end demo2;

architecture Behavioral of demo2 is

signal button : std_logic;
signal s3,s2,s1,s0 : std_logic_vector(3 downto 0);
signal ss3,ss2,ss1,ss0 : std_logic_vector(3 downto 0);
signal data3,data2,data1,data0 : std_logic_vector(3 downto 0);
signal data : std_logic_vector(3 downto 0);
signal clk1,clk1k : std_logic;
signal s_button : std_logic_vector(1 downto 0);

begin
process(ibutton,clk1)
variable t : std_logic_vector(1 downto 0);
begin
   if ibutton='1' then t:="00";
	elsif rising_edge(clk1) then
	   if t<"11" then t:=t+1;
		end if;
	end if;
	button<=(t(1)xor t(0));
end process;

process(clk)
variable cnt : integer range 0 to 50000;
begin
   if rising_edge(clk) then cnt:=cnt+1;
	   if cnt<25000 then clk1k<='0';
		elsif cnt<50000 then clk1k<='1';
		else cnt:=0;clk1k<='1';
		end if;
   end if;
end process;

process(clk1k)
variable cnt : integer range 0 to 100;
begin
   if rising_edge(clk1k) then	cnt:=cnt+1;
	   if cnt<50 then clk1<='0';
		elsif cnt<100 then clk1<='1';
		else clk1<='1';cnt:=0;
		end if;
   end if;
end process;

--mode 2
process(imode(1),button)
begin
   if imode(1)='1' then s_button<="00";
   elsif rising_edge(button) then 
	   if s_button<"11" then s_button<=s_button+1;
		else s_button<="01";
		end if;
	end if;
end process;

process(s_button,clk1)
begin
 if clk1'event and clk1='1' then
   if s_button="01" then 
	   --if rising_edge(clk1) then 
			if s0="1001" then s0<="0000";
			   if s1="1001" then s1<="0000";
				   if s2="1001" then s2<="0000";
					   if s3="1001" then s3<="0000";
						else s3<=s3+1;
						end if;
					else s2<=s2+1;
					end if;
				else s1<=s1+1;
				end if;
			else s0<=s0+1;
			end if;
		
	elsif s_button="10" then null;
	elsif s_button="11" then s0<="0000";s1<="0000";s2<="0000";s3<="0000";
	end if;
	end if;
end process;

--mode 3
process(imode(2),button)
begin
   if imode(2)='1' then ss0<="0000";ss1<="0000";ss2<="0000";ss3<="0000";
   elsif rising_edge(button) then
		if ss0="1001" then ss0<="0000";
			if ss1="1001" then ss1<="0000";
				if ss2="1001" then ss2<="0000";
					if ss3="1001" then ss3<="0000";
				   else ss3<=ss3+1;
					end if;
				else ss2<=ss2+1;
				end if;
			else ss1<=ss1+1;
			end if;
		else ss0<=ss0+1;
		end if;
	end if;
end process;
	    
process(imode,s3, s2, s1, s0, ss3, ss2, ss1, ss0)
begin
   case imode is
	when "110"=> cs<='1';cs1<='0'; 
	             data3<="1000";data2<="0001";data1<="0010";data0<="0100";
	when "101"=> cs<='1';cs<='1';cs1<='0';
	             data3<=s3;data2<=s2;data1<=s1;data0<=s0;
   when "011"=>  cs<='1';cs<='1';cs1<='0';
	             data3<=ss3;data2<=ss2;data1<=ss1;data0<=ss0;
	when others=>data3<="1111";data2<="1111";data1<="1111";data0<="1111";cs<='1';cs1<='1';
	end case;
end process;

process(clk1k)
variable c : integer range 0 to 3;
begin
   if rising_edge(clk1k) then	c:=c+1;
	   if c=0 then data<=data0;led_shift<="1110";
		elsif c=1 then data<=data1;led_shift<="1101";
		elsif c=2 then data<=data2;led_shift<="1011";
		else data<=data3;led_shift<="0111";
		end if;
   end if ;
end process;

process(data)
begin
   case data is
	when "0000"=>led<="00000011";                 
   when "0001" =>led<="10011111";
   when "0010" =>led<="00100101";
   when "0011" =>led<="00001101";                  
   when "0100" =>led<="10011001";                 
   when "0101" =>led<="01001001";                 
   when "0110" =>led<="01000001";                 
   when "0111" =>led<="00011111";                  
   when "1000" =>led<="00000001";                  
   when "1001" =>led<="00001001";                                   
 when others =>
         led<="11111111";                
  end case;
end process;
end Behavioral;