button1.vhd

总体演示程序DEMO_FPGA.rar

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-- Company: 
-- Engineer:
--
-- Create Date:    17:57:36 03/24/05
-- Design Name:    
-- Module Name:    button1 - keyboards
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity button1 is
    Port ( clk : in std_logic;
           ibutton : in std_logic;
           obutton :out std_logic);
end button1;

architecture keyboards of button1 is

begin
process(clk,ibutton)
variable delay : std_logic_vector(7 downto 0);
begin
   if ibutton='1' then delay:="00000000";
   elsif rising_edge(clk) then
      if delay<"01111111" then delay:=delay+1; 
	 else delay:="10000000";
	 end if;
   end if;	      

   obutton<=delay(7);

end process;
end keyboards;