entity.cpp

总体演示程序DEMO_FPGA.rar

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /___/   /      
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////


#include "ieee/vital_timing/vital_timing.h"
#include "ieee/vital_primitives/vital_primitives.h"
#include "ieee/std_logic_1164/std_logic_1164.h"
#include "simprim.auxlib/x_one/entity.h"

static const char *entFileName = "L:/H.39/rtf/vhdl/src/simprims/simprim_VITAL.vhd";
#ifdef _MSC_VER
#pragma warning(disable: 4355)
#endif

Simprim_x_one::Simprim_x_one(const char *name, const char* ArchName, const char* fileName, int numOfLine): HSim__s6(false,name,"X_ONE", ArchName, fileName, HSim::VhdlDesignEntity, numOfLine + 0)

{
  SE[0].initialize("o", &HSimStdLogic::Std_ulogic, this, HSim::PortSigOut, HSimSA::charToMem(3));
  ;
  ;
  SetPorts();
 
}

Simprim_x_one::~Simprim_x_one()
{
}

void Simprim_x_one::SetPorts()
{
}

void Simprim_x_one::constructEntityObject()
{
;
}