entity.cpp

总体演示程序DEMO_FPGA.rar

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /___/   /      
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////


#include "ieee/vital_timing/vital_timing.h"
#include "ieee/vital_primitives/vital_primitives.h"
#include "ieee/std_logic_1164/std_logic_1164.h"
#include "simprim.auxlib/x_or2/entity.h"

static const char *entFileName = "L:/H.39/rtf/vhdl/src/simprims/simprim_VITAL.vhd";
#ifdef _MSC_VER
#pragma warning(disable: 4355)
#endif

Simprim_x_or2::gDk::gDk() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_or2::gDt::gDt() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_or2::gDA::gDA() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_or2::gDH::gDH() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_or2::Simprim_x_or2(const char *name, const char* ArchName, const char* fileName,     const char * vXon,     const char * vMsgon,     const char * vTipd_i0,     const char * vTipd_i1,     const char * vTpd_i0_o,     const char * vTpd_i1_o, int numOfLine): HSim__s6(false,name,"X_OR2", ArchName, fileName, HSim::VhdlDesignEntity, numOfLine + 0)
, t152(0) 
{
  new(&Dc) HSim__s4("xon", vXon?vXon:HSimSA::charToMem(1), &HSimStandardPkg::Boolean);
  ;
  new(&De) HSim__s4("msgon", vMsgon?vMsgon:HSimSA::charToMem(1), &HSimStandardPkg::Boolean);
  ;
  new(&Dk) HSim__s4("tipd_i0", vTipd_i0?vTipd_i0:(gDk().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&Dt) HSim__s4("tipd_i1", vTipd_i1?vTipd_i1:(gDt().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&DA) HSim__s4("tpd_i0_o", vTpd_i0_o?vTpd_i0_o:(gDA().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&DH) HSim__s4("tpd_i1_o", vTpd_i1_o?vTpd_i1_o:(gDH().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  SE[0].initialize("o", &HSimStdLogic::Std_ulogic, this, HSim::PortSigOut);
  ;
  SE[0].setDefaultValue((char *)0);
;
  SE[1].initialize("i0", &HSimStdLogic::Std_ulogic, this, HSim::PortSigIn);
  ;
  SE[1].setDefaultValue((char *)0);
;
  SE[2].initialize("i1", &HSimStdLogic::Std_ulogic, this, HSim::PortSigIn);
  ;
  SE[2].setDefaultValue((char *)0);
;
  SetPorts();
    addVar(&Dc);
    addVar(&De);
    addVar(&Dk);
    addVar(&Dt);
    addVar(&DA);
    addVar(&DH);
 
}

Simprim_x_or2::~Simprim_x_or2()
{
}

void Simprim_x_or2::SetPorts()
{
}

void Simprim_x_or2::constructEntityObject()
{
;
}