entity.cpp

总体演示程序DEMO_FPGA.rar

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /___/   /      
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

static const char le0[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};

#include "ieee/vital_timing/vital_timing.h"
#include "ieee/vital_primitives/vital_primitives.h"
#include "ieee/numeric_std/numeric_std.h"
#include "ieee/std_logic_1164/std_logic_1164.h"
#include "simprim.auxlib/x_lut4/entity.h"

static const char *entFileName = "L:/H.39/rtf/vhdl/src/simprims/simprim_VITAL.vhd";
#ifdef _MSC_VER
#pragma warning(disable: 4355)
#endif

Simprim_x_lut4::gDm::gDm() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_lut4::gDu::gDu() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_lut4::gDB::gDB() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_lut4::gDI::gDI() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_lut4::gDQ::gDQ() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_lut4::gDX::gDX() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_lut4::gD14::gD14() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_lut4::gD1b::gD1b() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_lut4::Simprim_x_lut4(const char *name, const char* ArchName, const char* fileName,     const char * vXon,     const char * vMsgon,     const char * vTipd_adr0,     const char * vTipd_adr1,     const char * vTipd_adr2,     const char * vTipd_adr3,     const char * vTpd_adr0_o,     const char * vTpd_adr1_o,     const char * vTpd_adr2_o,     const char * vTpd_adr3_o,     const char * vInit, HSimConstraints * constrInit, int numOfLine): HSim__s6(false,name,"X_LUT4", ArchName, fileName, HSim::VhdlDesignEntity, numOfLine + 0)
, t154(0) 
{
  new(&Dd) HSim__s4("xon", vXon?vXon:HSimSA::charToMem(1), &HSimStandardPkg::Boolean);
  ;
  new(&Df) HSim__s4("msgon", vMsgon?vMsgon:HSimSA::charToMem(1), &HSimStandardPkg::Boolean);
  ;
  new(&Dm) HSim__s4("tipd_adr0", vTipd_adr0?vTipd_adr0:(gDm().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&Du) HSim__s4("tipd_adr1", vTipd_adr1?vTipd_adr1:(gDu().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&DB) HSim__s4("tipd_adr2", vTipd_adr2?vTipd_adr2:(gDB().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&DI) HSim__s4("tipd_adr3", vTipd_adr3?vTipd_adr3:(gDI().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&DQ) HSim__s4("tpd_adr0_o", vTpd_adr0_o?vTpd_adr0_o:(gDQ().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&DX) HSim__s4("tpd_adr1_o", vTpd_adr1_o?vTpd_adr1_o:(gDX().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&D14) HSim__s4("tpd_adr2_o", vTpd_adr2_o?vTpd_adr2_o:(gD14().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&D1b) HSim__s4("tpd_adr3_o", vTpd_adr3_o?vTpd_adr3_o:(gD1b().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&D1h) HSim__s4("init", vInit?vInit:le0, constrInit?constrInit:MKConstr(0, 15, HSim::TO), &HSimStandardPkg::Bit_vector);
  ;
  SE[0].initialize("o", &HSimStdLogic::Std_ulogic, this, HSim::PortSigOut);
  ;
  SE[0].setDefaultValue((char *)0);
;
  SE[1].initialize("adr0", &HSimStdLogic::Std_ulogic, this, HSim::PortSigIn);
  ;
  SE[1].setDefaultValue((char *)0);
;
  SE[2].initialize("adr1", &HSimStdLogic::Std_ulogic, this, HSim::PortSigIn);
  ;
  SE[2].setDefaultValue((char *)0);
;
  SE[3].initialize("adr2", &HSimStdLogic::Std_ulogic, this, HSim::PortSigIn);
  ;
  SE[3].setDefaultValue((char *)0);
;
  SE[4].initialize("adr3", &HSimStdLogic::Std_ulogic, this, HSim::PortSigIn);
  ;
  SE[4].setDefaultValue((char *)0);
;
  SetPorts();
    addVar(&Dd);
    addVar(&Df);
    addVar(&Dm);
    addVar(&Du);
    addVar(&DB);
    addVar(&DI);
    addVar(&DQ);
    addVar(&DX);
    addVar(&D14);
    addVar(&D1b);
    addVar(&D1h);
 
}

Simprim_x_lut4::~Simprim_x_lut4()
{
}

void Simprim_x_lut4::SetPorts()
{
}

void Simprim_x_lut4::constructEntityObject()
{
;
}