entity.cpp

总体演示程序DEMO_FPGA.rar

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /___/   /      
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////


#include "simprim.auxlib/vpackage/vpackage.h"
#include "ieee/vital_primitives/vital_primitives.h"
#include "ieee/vital_timing/vital_timing.h"
#include "ieee/std_logic_1164/std_logic_1164.h"
#include "simprim.auxlib/x_ff/entity.h"

static const char *entFileName = "L:/H.39/rtf/vhdl/src/simprims/simprim_VITAL.vhd";
#ifdef _MSC_VER
#pragma warning(disable: 4355)
#endif

Simprim_x_ff::gDt::gDt() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_ff::gDA::gDA() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_ff::gDH::gDH() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_ff::gDP::gDP() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_ff::gDW::gDW() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_ff::gD13::gD13() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 100000LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 100000LL;
}

Simprim_x_ff::gD1a::gD1a() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_ff::gD1h::gD1h() {
    this->bufSize = 16;
    this->buf = HSimMemPool::getTransientMemory(this->bufSize);
  *(int64 *)(this->buf + (0 - 0) * 8) = 0LL;
  *(int64 *)(this->buf + (1 - 0) * 8) = 0LL;
}

Simprim_x_ff::Simprim_x_ff(const char *name, const char* ArchName, const char* fileName,     const char * vTimingcheckson,     const char * vXon,     const char * vMsgon,     const char * vInit,     const char * vTipd_ce,     const char * vTipd_clk,     const char * vTipd_i,     const char * vTipd_rst,     const char * vTipd_set,     const char * vTpd_clk_o,     const char * vTpd_rst_o,     const char * vTpd_set_o,     const char * vTsetup_i_clk_posedge_posedge,     const char * vTsetup_i_clk_negedge_posedge,     const char * vThold_i_clk_posedge_posedge,     const char * vThold_i_clk_negedge_posedge,     const char * vTsetup_ce_clk_posedge_posedge,     const char * vTsetup_ce_clk_negedge_posedge,     const char * vThold_ce_clk_posedge_posedge,     const char * vThold_ce_clk_negedge_posedge,     const char * vTrecovery_rst_clk_negedge_posedge,     const char * vThold_rst_clk_negedge_posedge,     const char * vTrecovery_set_clk_negedge_posedge,     const char * vThold_set_clk_negedge_posedge,     const char * vTicd_clk,     const char * vTisd_ce_clk,     const char * vTisd_i_clk,     const char * vTisd_rst_clk,     const char * vTisd_set_clk,     const char * vTperiod_clk_posedge,     const char * vTpw_rst_posedge,     const char * vTpw_set_posedge, int numOfLine): HSim__s6(false,name,"X_FF", ArchName, fileName, HSim::VhdlDesignEntity, numOfLine + 0)
, t153(0) 
{
  new(&De) HSim__s4("timingcheckson", vTimingcheckson?vTimingcheckson:HSimSA::charToMem(1), &HSimStandardPkg::Boolean);
  ;
  new(&Dg) HSim__s4("xon", vXon?vXon:HSimSA::charToMem(1), &HSimStandardPkg::Boolean);
  ;
  new(&Di) HSim__s4("msgon", vMsgon?vMsgon:HSimSA::charToMem(1), &HSimStandardPkg::Boolean);
  ;
  new(&Dm) HSim__s4("init", vInit?vInit:HSimSA::charToMem(0), &HSimStandardPkg::Bit);
  ;
  new(&Dt) HSim__s4("tipd_ce", vTipd_ce?vTipd_ce:(gDt().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&DA) HSim__s4("tipd_clk", vTipd_clk?vTipd_clk:(gDA().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&DH) HSim__s4("tipd_i", vTipd_i?vTipd_i:(gDH().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&DP) HSim__s4("tipd_rst", vTipd_rst?vTipd_rst:(gDP().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&DW) HSim__s4("tipd_set", vTipd_set?vTipd_set:(gDW().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&D13) HSim__s4("tpd_clk_o", vTpd_clk_o?vTpd_clk_o:(gD13().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&D1a) HSim__s4("tpd_rst_o", vTpd_rst_o?vTpd_rst_o:(gD1a().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&D1h) HSim__s4("tpd_set_o", vTpd_set_o?vTpd_set_o:(gD1h().getVal()), &IeeeVital_timing->Vitaldelaytype01);
  ;
  new(&D1p) HSim__s4("tsetup_i_clk_posedge_posedge", vTsetup_i_clk_posedge_posedge?vTsetup_i_clk_posedge_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D1s) HSim__s4("tsetup_i_clk_negedge_posedge", vTsetup_i_clk_negedge_posedge?vTsetup_i_clk_negedge_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D1v) HSim__s4("thold_i_clk_posedge_posedge", vThold_i_clk_posedge_posedge?vThold_i_clk_posedge_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D1y) HSim__s4("thold_i_clk_negedge_posedge", vThold_i_clk_negedge_posedge?vThold_i_clk_negedge_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D1B) HSim__s4("tsetup_ce_clk_posedge_posedge", vTsetup_ce_clk_posedge_posedge?vTsetup_ce_clk_posedge_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D1E) HSim__s4("tsetup_ce_clk_negedge_posedge", vTsetup_ce_clk_negedge_posedge?vTsetup_ce_clk_negedge_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D1H) HSim__s4("thold_ce_clk_posedge_posedge", vThold_ce_clk_posedge_posedge?vThold_ce_clk_posedge_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D1K) HSim__s4("thold_ce_clk_negedge_posedge", vThold_ce_clk_negedge_posedge?vThold_ce_clk_negedge_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D1N) HSim__s4("trecovery_rst_clk_negedge_posedge", vTrecovery_rst_clk_negedge_posedge?vTrecovery_rst_clk_negedge_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D1R) HSim__s4("thold_rst_clk_negedge_posedge", vThold_rst_clk_negedge_posedge?vThold_rst_clk_negedge_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D1U) HSim__s4("trecovery_set_clk_negedge_posedge", vTrecovery_set_clk_negedge_posedge?vTrecovery_set_clk_negedge_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D1X) HSim__s4("thold_set_clk_negedge_posedge", vThold_set_clk_negedge_posedge?vThold_set_clk_negedge_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D20) HSim__s4("ticd_clk", vTicd_clk?vTicd_clk:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D23) HSim__s4("tisd_ce_clk", vTisd_ce_clk?vTisd_ce_clk:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D26) HSim__s4("tisd_i_clk", vTisd_i_clk?vTisd_i_clk:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D29) HSim__s4("tisd_rst_clk", vTisd_rst_clk?vTisd_rst_clk:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D2c) HSim__s4("tisd_set_clk", vTisd_set_clk?vTisd_set_clk:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D2f) HSim__s4("tperiod_clk_posedge", vTperiod_clk_posedge?vTperiod_clk_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D2i) HSim__s4("tpw_rst_posedge", vTpw_rst_posedge?vTpw_rst_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  new(&D2m) HSim__s4("tpw_set_posedge", vTpw_set_posedge?vTpw_set_posedge:HSimSA::int64ToMem(0LL), &IeeeVital_timing->Vitaldelaytype);
  ;
  SE[0].initialize("o", &HSimStdLogic::Std_ulogic, this, HSim::PortSigOut);
  ;
  SE[0].setDefaultValue((char *)0);
;
  SE[1].initialize("ce", &HSimStdLogic::Std_ulogic, this, HSim::PortSigIn);
  ;
  SE[1].setDefaultValue((char *)0);
;
  SE[2].initialize("clk", &HSimStdLogic::Std_ulogic, this, HSim::PortSigIn);
  ;
  SE[2].setDefaultValue((char *)0);
;
  SE[3].initialize("i", &HSimStdLogic::Std_ulogic, this, HSim::PortSigIn);
  ;
  SE[3].setDefaultValue((char *)0);
;
  SE[4].initialize("rst", &HSimStdLogic::Std_ulogic, this, HSim::PortSigIn);
  ;
  SE[4].setDefaultValue((char *)0);
;
  SE[5].initialize("set", &HSimStdLogic::Std_ulogic, this, HSim::PortSigIn);
  ;
  SE[5].setDefaultValue((char *)0);
;
  SetPorts();
    addVar(&De);
    addVar(&Dg);
    addVar(&Di);
    addVar(&Dm);
    addVar(&Dt);
    addVar(&DA);
    addVar(&DH);
    addVar(&DP);
    addVar(&DW);
    addVar(&D13);
    addVar(&D1a);
    addVar(&D1h);
    addVar(&D1p);
    addVar(&D1s);
    addVar(&D1v);
    addVar(&D1y);
    addVar(&D1B);
    addVar(&D1E);
    addVar(&D1H);
    addVar(&D1K);
    addVar(&D1N);
    addVar(&D1R);
    addVar(&D1U);
    addVar(&D1X);
    addVar(&D20);
    addVar(&D23);
    addVar(&D26);
    addVar(&D29);
    addVar(&D2c);
    addVar(&D2f);
    addVar(&D2i);
    addVar(&D2m);
 
}

Simprim_x_ff::~Simprim_x_ff()
{
}

void Simprim_x_ff::SetPorts()
{
}

void Simprim_x_ff::constructEntityObject()
{
;
}