entity.h

总体演示程序DEMO_FPGA.rar

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /___/   /      
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

#ifndef H_Simprim_x_ff_H
#define H_Simprim_x_ff_H

#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif



class Simprim_x_ff: public HSim__s6 {

public:
HSim__s4 De;
HSim__s4 Dg;
HSim__s4 Di;
HSim__s4 Dm;
  char *t153;
HSim__s4 Dt;
HSim__s4 DA;
HSim__s4 DH;
HSim__s4 DP;
HSim__s4 DW;
HSim__s4 D13;
HSim__s4 D1a;
HSim__s4 D1h;
HSim__s4 D1p;
HSim__s4 D1s;
HSim__s4 D1v;
HSim__s4 D1y;
HSim__s4 D1B;
HSim__s4 D1E;
HSim__s4 D1H;
HSim__s4 D1K;
HSim__s4 D1N;
HSim__s4 D1R;
HSim__s4 D1U;
HSim__s4 D1X;
HSim__s4 D20;
HSim__s4 D23;
HSim__s4 D26;
HSim__s4 D29;
HSim__s4 D2c;
HSim__s4 D2f;
HSim__s4 D2i;
HSim__s4 D2m;
    HSim__s1 SE[6];
    Simprim_x_ff(const char *name, const char* ArchName, const char *fileName,     const char * vTimingcheckson=0,     const char * vXon=0,     const char * vMsgon=0,     const char * vInit=0,     const char * vTipd_ce=0,     const char * vTipd_clk=0,     const char * vTipd_i=0,     const char * vTipd_rst=0,     const char * vTipd_set=0,     const char * vTpd_clk_o=0,     const char * vTpd_rst_o=0,     const char * vTpd_set_o=0,     const char * vTsetup_i_clk_posedge_posedge=0,     const char * vTsetup_i_clk_negedge_posedge=0,     const char * vThold_i_clk_posedge_posedge=0,     const char * vThold_i_clk_negedge_posedge=0,     const char * vTsetup_ce_clk_posedge_posedge=0,     const char * vTsetup_ce_clk_negedge_posedge=0,     const char * vThold_ce_clk_posedge_posedge=0,     const char * vThold_ce_clk_negedge_posedge=0,     const char * vTrecovery_rst_clk_negedge_posedge=0,     const char * vThold_rst_clk_negedge_posedge=0,     const char * vTrecovery_set_clk_negedge_posedge=0,     const char * vThold_set_clk_negedge_posedge=0,     const char * vTicd_clk=0,     const char * vTisd_ce_clk=0,     const char * vTisd_i_clk=0,     const char * vTisd_rst_clk=0,     const char * vTisd_set_clk=0,     const char * vTperiod_clk_posedge=0,     const char * vTpw_rst_posedge=0,     const char * vTpw_set_posedge=0, int numOfLine = 0);
    ~Simprim_x_ff();
    void SetPorts();
    void constructEntityObject();

    class gDt : public HSimGenValCtor
    {
    public: 
        gDt();
    };

    class gDA : public HSimGenValCtor
    {
    public: 
        gDA();
    };

    class gDH : public HSimGenValCtor
    {
    public: 
        gDH();
    };

    class gDP : public HSimGenValCtor
    {
    public: 
        gDP();
    };

    class gDW : public HSimGenValCtor
    {
    public: 
        gDW();
    };

    class gD13 : public HSimGenValCtor
    {
    public: 
        gD13();
    };

    class gD1a : public HSimGenValCtor
    {
    public: 
        gD1a();
    };

    class gD1h : public HSimGenValCtor
    {
    public: 
        gD1h();
    };

};

#endif