entity.cpp

总体演示程序DEMO_FPGA.rar

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /___/   /      
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

static const char le0[] = "*";

#include "ieee/vital_timing/vital_timing.h"
#include "ieee/vital_primitives/vital_primitives.h"
#include "ieee/std_logic_1164/std_logic_1164.h"
#include "simprim.auxlib/x_roc/entity.h"

static const char *entFileName = "L:/H.39/rtf/vhdl/src/simprims/simprim_VITAL.vhd";
#ifdef _MSC_VER
#pragma warning(disable: 4355)
#endif

Simprim_x_roc::Simprim_x_roc(const char *name, const char* ArchName, const char* fileName,     const char * vRoc_width,     const char * vInstancepath, HSimConstraints * constrInstancepath, int numOfLine): HSim__s6(false,name,"X_ROC", ArchName, fileName, HSim::VhdlDesignEntity, numOfLine + 0)

{
  new(&De) HSim__s4("roc_width", vRoc_width?vRoc_width:HSimSA::int64ToMem(100000000LL), &HSimStandardPkg::Time);
  ;
  new(&Di) HSim__s4("instancepath", vInstancepath?vInstancepath:le0, constrInstancepath?constrInstancepath:MKConstr(1, 1, HSim::TO), &HSimStandardPkg::String);
  ;
  SE[0].initialize("o", &HSimStdLogic::Std_ulogic, this, HSim::PortSigOut);
  ;
  SE[0].setDefaultValue((char *)0);
;
  SetPorts();
    addVar(&De);
    addVar(&Di);
 
}

Simprim_x_roc::~Simprim_x_roc()
{
}

void Simprim_x_roc::SetPorts()
{
}

void Simprim_x_roc::constructEntityObject()
{
;
}