top_mode_cymometer.syr

总体演示程序DEMO_FPGA.rar

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_mode_cymometer, actual ratio is 5.
FlipFlop u1/current_state_FFd1 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top_mode_cymometer.ngr
Top Level Output File Name         : top_mode_cymometer
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 29

Macro Statistics :
# Registers                        : 8
#      1-bit register              : 1
#      24-bit register             : 1
#      4-bit register              : 6
# Adders/Subtractors               : 6
#      4-bit adder                 : 6

Cell Usage :
# BELS                             : 133
#      LUT2                        : 9
#      LUT2_D                      : 2
#      LUT2_L                      : 1
#      LUT3                        : 11
#      LUT3_D                      : 2
#      LUT3_L                      : 1
#      LUT4                        : 68
#      LUT4_D                      : 7
#      LUT4_L                      : 26
#      MUXF5                       : 5
#      VCC                         : 1
# FlipFlops/Latches                : 61
#      FD                          : 17
#      FDE                         : 24
#      FDR                         : 1
#      FDS                         : 11
#      LD                          : 8
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 27
#      IBUF                        : 19
#      OBUF                        : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100epq208-6 

 Number of Slices:                      70  out of   1200     5%  
 Number of Slice Flip Flops:            61  out of   2400     2%  
 Number of 4 input LUTs:               127  out of   2400     5%  
 Number of bonded IOBs:                 29  out of    146    19%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
u0/_n0001(u0/_n00012:O)            | NONE(*)(u0/dout_3)     | 8     |
clka                               | BUFGP                  | 52    |
clkb                               | BUFGP                  | 1     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 10.711ns (Maximum Frequency: 93.362MHz)
   Minimum input arrival time before clock: 10.791ns
   Maximum output required time after clock: 6.613ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clka'
  Clock period: 10.711ns (frequency: 93.362MHz)
  Total number of paths / destination ports: 805 / 87
-------------------------------------------------------------------------
Delay:               10.711ns (Levels of Logic = 4)
  Source:            u1/cnt2_0 (FF)
  Destination:       u1/cnt6_3 (FF)
  Source Clock:      clka rising
  Destination Clock: clka rising

  Data Path: u1/cnt2_0 to u1/cnt6_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               7   0.992   1.950  u1/cnt2_0 (u1/cnt2_0)
     LUT4_D:I0->O         10   0.468   2.250  u1/_n00221 (u1/_n0022)
     LUT4:I2->O            8   0.468   2.050  u1/_n0014<0>361_SW0 (N822)
     LUT4_L:I3->LO         1   0.468   0.100  u1/_n0014<3>25 (CHOICE1656)
     LUT4:I2->O            1   0.468   0.920  u1/_n0014<3>50 (CHOICE1660)
     FDS:S                     0.577          u1/cnt6_3
    ----------------------------------------
    Total                     10.711ns (3.441ns logic, 7.270ns route)
                                       (32.1% logic, 67.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clkb'
  Clock period: 3.089ns (frequency: 323.729MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               3.089ns (Levels of Logic = 0)
  Source:            u1/kd (FF)
  Destination:       u1/kd (FF)
  Source Clock:      clkb rising
  Destination Clock: clkb rising

  Data Path: u1/kd to u1/kd
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              4   0.992   1.520  u1/kd (u1/kd)
     FDR:R                     0.577          u1/kd
    ----------------------------------------
    Total                      3.089ns (1.569ns logic, 1.520ns route)
                                       (50.8% logic, 49.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'u0/_n00012:O'
  Total number of paths / destination ports: 76 / 8
-------------------------------------------------------------------------
Offset:              10.791ns (Levels of Logic = 6)
  Source:            addr<2> (PAD)
  Destination:       u0/dout_2 (LATCH)
  Destination Clock: u0/_n00012:O falling

  Data Path: addr<2> to u0/dout_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            14   0.797   2.650  addr_2_IBUF (addr_2_IBUF)
     LUT2:I1->O            4   0.468   1.520  u0/Ker211 (u0/N21)
     LUT4:I0->O            1   0.468   0.920  u0/_n0002<3>67 (CHOICE1459)
     LUT4:I3->O            1   0.468   0.920  u0/_n0002<3>71 (CHOICE1460)
     LUT4:I0->O            1   0.468   0.920  u0/_n0002<3>107_SW0 (N832)
     LUT4:I3->O            1   0.468   0.000  u0/_n0002<3>107 (u0/_n0002<3>)
     LD:D                      0.724          u0/dout_3
    ----------------------------------------
    Total                     10.791ns (3.861ns logic, 6.930ns route)
                                       (35.8% logic, 64.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clka'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset:              3.309ns (Levels of Logic = 2)
  Source:            tclk (PAD)
  Destination:       u1/current_state_FFd1 (FF)
  Destination Clock: clka rising

  Data Path: tclk to u1/current_state_FFd1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   0.797   1.320  tclk_IBUF (tclk_IBUF)
     LUT4:I3->O            1   0.468   0.000  u1/current_state_FFd3-In1 (u1/N16)
     FDS:D                     0.724          u1/current_state_FFd3
    ----------------------------------------
    Total                      3.309ns (1.989ns logic, 1.320ns route)
                                       (60.1% logic, 39.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'u0/_n00012:O'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              6.613ns (Levels of Logic = 1)
  Source:            u0/dout_7 (LATCH)
  Destination:       dout<7> (PAD)
  Source Clock:      u0/_n00012:O falling

  Data Path: u0/dout_7 to dout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   1.091   0.920  u0/dout_7 (u0/dout_7)
     OBUF:I->O                 4.602          dout_7_OBUF (dout<7>)
    ----------------------------------------
    Total                      6.613ns (5.693ns logic, 0.920ns route)
                                       (86.1% logic, 13.9% route)

=========================================================================
CPU : 21.03 / 21.91 s | Elapsed : 21.00 / 22.00 s
 
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Total memory usage is 90532 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    3 (   0 filtered)