top_mode_cymometer.syr

总体演示程序DEMO_FPGA.rar

Release 7.1.01i - xst H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: top_mode_cymometer.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "top_mode_cymometer.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "top_mode_cymometer"
Output Format                      : NGC
Target Device                      : xc2s100e-6-pq208

---- Source Options
Top Module Name                    : top_mode_cymometer
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : top_mode_cymometer.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/DEMO_FPGA/page4.vhd" in Library work.
Architecture behavioral of Entity page4 is up to date.
Compiling vhdl file "E:/DEMO_FPGA/mode_cymometer.vhd" in Library work.
Architecture behavioral of Entity mode_cymometer is up to date.
Compiling vhdl file "E:/DEMO_FPGA/top_mode_cymometer.vhd" in Library work.
Entity <top_mode_cymometer> compiled.
Entity <top_mode_cymometer> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_mode_cymometer> (Architecture <Behavioral>).
Entity <top_mode_cymometer> analyzed. Unit <top_mode_cymometer> generated.

Analyzing Entity <page4> (Architecture <behavioral>).
WARNING:Xst:819 - "E:/DEMO_FPGA/page4.vhd" line 42: The following signals are missing in the process sensitivity list:
   dint<23>, dint<22>, dint<21>, dint<20>, dint<19>, dint<18>, dint<17>, dint<16>, dint<15>, dint<14>, dint<13>, dint<12>, dint<11>, dint<10>, dint<9>, dint<8>, dint<7>, dint<6>, dint<5>, dint<4>, dint<3>, dint<2>, dint<1>, dint<0>.
Entity <page4> analyzed. Unit <page4> generated.

Analyzing Entity <mode_cymometer> (Architecture <behavioral>).
Entity <mode_cymometer> analyzed. Unit <mode_cymometer> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <mode_cymometer>.
    Related source file is "E:/DEMO_FPGA/mode_cymometer.vhd".
INFO:Xst:1799 - State st5 is never reached in FSM <current_state>.
INFO:Xst:1799 - State st6 is never reached in FSM <current_state>.
    Found finite state machine <FSM_0> for signal <current_state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 9                                              |
    | Inputs             | 2                                              |
    | Outputs            | 3                                              |
    | Clock              | clka (rising_edge)                             |
    | Power Up State     | st0                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 24-bit register for signal <dout>.
    Found 4-bit adder for signal <$n0015> created at line 100.
    Found 4-bit adder for signal <$n0016> created at line 99.
    Found 4-bit adder for signal <$n0017> created at line 98.
    Found 4-bit adder for signal <$n0018> created at line 97.
    Found 4-bit adder for signal <$n0019> created at line 96.
    Found 4-bit adder for signal <$n0020> created at line 95.
    Found 4-bit register for signal <cnt1>.
    Found 4-bit register for signal <cnt2>.
    Found 4-bit register for signal <cnt3>.
    Found 4-bit register for signal <cnt4>.
    Found 4-bit register for signal <cnt5>.
    Found 4-bit register for signal <cnt6>.
    Found 1-bit register for signal <kd>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  49 D-type flip-flop(s).
	inferred   6 Adder/Subtractor(s).
Unit <mode_cymometer> synthesized.


Synthesizing Unit <page4>.
    Related source file is "E:/DEMO_FPGA/page4.vhd".
WARNING:Xst:737 - Found 8-bit latch for signal <dout>.
Unit <page4> synthesized.


Synthesizing Unit <top_mode_cymometer>.
    Related source file is "E:/DEMO_FPGA/top_mode_cymometer.vhd".
Unit <top_mode_cymometer> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <current_state[1:3]> with gray encoding.
-------------------
 State | Encoding
-------------------
 st0   | 000
 st1   | 001
 st2   | 011
 st3   | 110
 st4   | 010
 st5   | unreached
 st6   | unreached
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 6
 4-bit adder                       : 6
# Registers                        : 11
 1-bit register                    : 4
 24-bit register                   : 1
 4-bit register                    : 6
# Latches                          : 1
 8-bit latch                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <top_mode_cymometer> ...

Optimizing unit <mode_cymometer> ...

Optimizing unit <page4> ...
Loading device for application Rf_Device from file '2s100e.nph' in environment E:/Program/EDA/Xilinx.