coregen.rsp

来自「总体演示程序DEMO_FPGA.rar」· RSP 代码 · 共 13 行

NEWPROJECT e:\demo_fpga
SETPROJECT e:\demo_fpga
SET BusFormat = BusFormatAngleBracketNotRipped
SET devicefamily = Spartan2
SET device = xc2s100e
SET package = pq208
SET speedgrade = -6
SET FlowVendor = Foundation_iSE
SET OutputOption = OutputProducts
SET OutputProducts = ImpNetlist;ASYSymbol;VHDLSim;VerilogSim
SET SimulationOutputProducts = Verilog VHDL
SET LockProjectProps = false