electronic_organ.vhd

总体演示程序DEMO_FPGA.rar

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    05:10:09 03/25/05
-- Design Name:    
-- Module Name:    electronic_organ - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity electronic_organ is
   port(clk : in std_logic;
        button : in std_logic_vector(3 downto 0);
	   tone : out std_logic);
end electronic_organ;

architecture Behavioral of electronic_organ is

signal div_cnt : integer range 0 to 199999;

begin
   with button select
   div_cnt <= 190100 when "0111",
              170600 when "1011",
		    151950 when "1101",
		    143250 when "1110",
		    0 when others;
		    
process(clk)
variable cnt : integer range 0 to 199999;
begin 
   if rising_edge(clk) then cnt:=cnt+1;
      if div_cnt=0 then tone<='1';
	 elsif cnt<div_cnt/2 then tone<='0';
	 elsif cnt<div_cnt then tone<='1';
	 else cnt:=0;
	 end if;
   end if;
end process;
end Behavioral;