digital_clk.syr

总体演示程序DEMO_FPGA.rar

Release 7.1.01i - xst H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: digital_clk.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "digital_clk.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "digital_clk"
Output Format                      : NGC
Target Device                      : xc2s100e-6-pq208

---- Source Options
Top Module Name                    : digital_clk
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : digital_clk.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/DEMO_FPGA/digital_clk.vhd" in Library work.
Entity <digital_clk> compiled.
Entity <digital_clk> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <digital_clk> (Architecture <behavioral>).
Entity <digital_clk> analyzed. Unit <digital_clk> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <digital_clk>.
    Related source file is "E:/DEMO_FPGA/digital_clk.vhd".
    Found 4-bit adder for signal <$n0000> created at line 45.
    Found 4-bit adder for signal <$n0001> created at line 46.
    Found 4-bit adder for signal <$n0002> created at line 47.
    Found 4-bit adder for signal <$n0003> created at line 49.
    Found 4-bit adder for signal <$n0008> created at line 51.
    Found 4-bit adder for signal <$n0017> created at line 53.
    Found 1-bit 4-to-1 multiplexer for signal <$n0031>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0032>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0039>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0040>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0041>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0042>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0048>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0049>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0050>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0051>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0057>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0058>.
    Found 8-bit register for signal <c1>.
    Found 8-bit register for signal <c2>.
    Found 8-bit register for signal <c3>.
    Summary:
	inferred  24 D-type flip-flop(s).
	inferred   6 Adder/Subtractor(s).
	inferred  12 Multiplexer(s).
Unit <digital_clk> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 6
 4-bit adder                       : 6
# Registers                        : 24
 1-bit register                    : 24
# Multiplexers                     : 12
 1-bit 4-to-1 multiplexer          : 12

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <digital_clk> ...
Loading device for application Rf_Device from file '2s100e.nph' in environment E:/Program/EDA/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block digital_clk, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : digital_clk.ngr
Top Level Output File Name         : digital_clk
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 26

Macro Statistics :
# Registers                        : 24
#      1-bit register              : 24
# Multiplexers                     : 12
#      1-bit 4-to-1 multiplexer    : 12
# Adders/Subtractors               : 6
#      4-bit adder                 : 6

Cell Usage :
# BELS                             : 55
#      INV                         : 3
#      LUT2                        : 4
#      LUT2_D                      : 1
#      LUT3                        : 11
#      LUT3_D                      : 1
#      LUT4                        : 25
#      LUT4_D                      : 1
#      LUT4_L                      : 9
# FlipFlops/Latches                : 24
#      FDC                         : 2
#      FDCE                        : 18
#      FDP                         : 2
#      FDPE                        : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 25
#      IBUF                        : 1
#      OBUF                        : 24
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100epq208-6 

 Number of Slices:                      28  out of   1200     2%  
 Number of Slice Flip Flops:            24  out of   2400     1%  
 Number of 4 input LUTs:                52  out of   2400     2%  
 Number of bonded IOBs:                 26  out of    146    17%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 24    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.523ns (Maximum Frequency: 105.009MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.944ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 9.523ns (frequency: 105.009MHz)
  Total number of paths / destination ports: 419 / 44
-------------------------------------------------------------------------
Delay:               9.523ns (Levels of Logic = 3)
  Source:            c1_0 (FF)
  Destination:       c2_7 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: c1_0 to c2_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              8   0.992   2.050  c1_0 (c1_0)
     LUT3:I1->O            1   0.468   0.920  Ker17_SW1 (N108)
     LUT4:I3->O            7   0.468   1.950  Ker151 (N15)
     LUT4:I0->O            4   0.468   1.520  _n0087 (_n0087)
     FDCE:CE                   0.687          c2_5
    ----------------------------------------
    Total                      9.523ns (3.083ns logic, 6.440ns route)
                                       (32.4% logic, 67.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 24 / 24
-------------------------------------------------------------------------
Offset:              7.944ns (Levels of Logic = 1)
  Source:            c2_0 (FF)
  Destination:       om<0> (PAD)
  Source Clock:      clk rising

  Data Path: c2_0 to om<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            11   0.992   2.350  c2_0 (c2_0)
     OBUF:I->O                 4.602          om_0_OBUF (om<0>)
    ----------------------------------------
    Total                      7.944ns (5.594ns logic, 2.350ns route)
                                       (70.4% logic, 29.6% route)

=========================================================================
CPU : 13.17 / 15.76 s | Elapsed : 14.00 / 15.00 s
 
--> 

Total memory usage is 88484 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)