mux_1.vhd

来自「总体演示程序DEMO_FPGA.rar」· VHDL 代码 · 共 39 行

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-- Company: 
-- Engineer:
--
-- Create Date:    02:44:13 03/25/05
-- Design Name:    
-- Module Name:    mux_1 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux_1 is
end mux_1;

architecture Behavioral of mux_1 is

begin


end Behavioral;