address_gen.vhd

来自「总体演示程序DEMO_FPGA.rar」· VHDL 代码 · 共 92 行

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-- Company: 
-- Engineer:
--
-- Create Date:    05:18:49 03/24/05
-- Design Name:    
-- Module Name:    address_gen - page_information
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity address_gen is
   generic(hold_a : integer := 4);

   port(clk   : in std_logic;
        reset : in std_logic;
	 gen_addr: out std_logic_vector(4 downto 0));

end address_gen;

architecture page_information of address_gen is

type state is (st0,st1,st2,st3,st4);
signal current_state : state;

begin
process(clk,reset)
variable delay_a : integer range 1 to hold_a;
variable reg_c : std_logic_vector(5 downto 0);
variable reg_d : std_logic_vector(5 downto 0);
begin
   if reset='1' then 
	         delay_a:=1;
		    reg_c:="111111";
              current_state<=st0;
   elsif rising_edge(clk) then 
      case current_state is
	 when st0=>
		    if delay_a<hold_a then 
		       delay_a:=delay_a+1;
		    else 
		       delay_a:=1;
		       current_state<=st1;
		    end if;

      when st1=>
	            current_state<=st2;

      when st2=>
		    if reg_c<"010000" then
		       reg_c:=reg_c+1;
		    else
		       current_state<=st3;
		    end if;
      
	 when st3=>
	            current_state<=st4;

      when st4=>
	         if reg_c<"100000" then
		       reg_c:=reg_c+1;
		    else
		       current_state<=st1;
		    end if;
      
	 when others=>
	         current_state<=st0;
      end case;
   end if;

   reg_d:=reg_c-1;

   gen_addr<=reg_d(4 downto 0);

end process;

end page_information;