electronic_organ.twr

总体演示程序DEMO_FPGA.rar

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Release 7.1.01i Trace H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

E:/Program/EDA/Xilinx/bin/nt/trce.exe -ise e:\demo_fpga\DEMO_FPGA.ise -intstyle
ise -e 3 -l 3 -s 6 -xml electronic_organ electronic_organ.ncd -o
electronic_organ.twr electronic_organ.pcf


Design file:              electronic_organ.ncd
Physical constraint file: electronic_organ.pcf
Device,speed:             xc2s100e,-6 (PRODUCTION 1.18 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
button<0>   |   11.786(R)|   -2.714(R)|clk_BUFGP         |   0.000|
button<1>   |   11.760(R)|   -2.688(R)|clk_BUFGP         |   0.000|
button<2>   |   12.128(R)|   -3.056(R)|clk_BUFGP         |   0.000|
button<3>   |   12.360(R)|   -3.288(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
tone        |    6.436(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |   12.426|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Fri Mar 25 05:39:04 2005
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Peak Memory Usage: 69 MB