dfgf.tbw

总体演示程序DEMO_FPGA.rar

version 3
e:\demo_fpga\digital_clk.vhd
digital_clk
VHDL
VHDL
dfgf.xwv
Clocked
-
-
1000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
10000000
10000000
1000000
1000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
ireset
clk
oh
clk
om
clk
os
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
oh_DIFF
om_DIFF
os_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
ireset
oh
om
os
SIGNAL_ORDER_END
-X-X-X-