demo_all.syr

总体演示程序DEMO_FPGA.rar

#      LUT1_L                      : 12
#      LUT2                        : 290
#      LUT2_L                      : 1
#      LUT3                        : 232
#      LUT3_L                      : 5
#      LUT4                        : 607
#      LUT4_D                      : 1
#      LUT4_L                      : 23
#      MUXCY                       : 785
#      MUXF5                       : 58
#      MUXF6                       : 8
#      VCC                         : 2
#      XORCY                       : 571
# FlipFlops/Latches                : 746
#      FD                          : 60
#      FDC                         : 171
#      FDC_1                       : 12
#      FDCE                        : 15
#      FDCP                        : 8
#      FDCPE                       : 20
#      FDE                         : 145
#      FDE_1                       : 14
#      FDP_1                       : 1
#      FDPE                        : 8
#      FDR                         : 158
#      FDRE                        : 7
#      FDRSE                       : 18
#      FDS                         : 30
#      FDSE                        : 2
#      LD                          : 77
# RAMS                             : 3
#      RAMB4_S16                   : 1
#      RAMB4_S8                    : 2
# Clock Buffers                    : 4
#      BUFG                        : 3
#      BUFGP                       : 1
# IO Buffers                       : 46
#      IBUF                        : 17
#      OBUF                        : 29
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100epq208-6 

 Number of Slices:                    1056  out of   1200    88%  
 Number of Slice Flip Flops:           746  out of   2400    31%  
 Number of 4 input LUTs:              1670  out of   2400    69%  
 Number of bonded IOBs:                 47  out of    146    32%  
 Number of BRAMs:                        3  out of     10    30%  
 Number of GCLKs:                        4  out of      4   100%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+---------------------------+-------+
Clock Signal                       | Clock buffer(FF name)     | Load  |
-----------------------------------+---------------------------+-------+
_n0123(_n0123:O)                   | NONE(*)(but1)             | 3     |
_n0125(_n01251:O)                  | NONE(*)(tone)             | 1     |
_n0124(_n01241:O)                  | NONE(*)(mode1_1)          | 8     |
_n0002(_n00021:O)                  | NONE(*)(button3a_0)       | 8     |
_n0122(_n01222:O)                  | NONE(*)(cs_0)             | 10    |
_n0003(_n00031:O)                  | NONE(*)(button1_1)        | 8     |
u4/clk1k:Q                         | BUFG                      | 93    |
u4/u4/u1/_n0001(u4/u4/u1/_n00012:O)| NONE(*)(u4/u4/u1/dout_0)  | 8     |
clk                                | BUFGP                     | 220   |
u4/u8/_n0001(u4/u8/_n00012:O)      | NONE(*)(u4/u8/dout_0)     | 8     |
u4/u5/u0/_n0001(u4/u5/u0/_n00012:O)| NONE(*)(u4/u5/u0/dout_3)  | 8     |
u4/u4/u0/sclkb:Q                   | NONE                      | 8     |
u4/clk1:Q                          | NONE                      | 9     |
u4/u4/u0/sclka:Q                   | NONE                      | 8     |
u2/clk1:Q                          | NONE                      | 18    |
u4/reg_clk1k1(u4/reg_clk1k2:O)     | BUFG(*)(u4/u7/dout_lcd_13)| 108   |
u3/button(u3/button1:O)            | NONE(*)(u3/cnt1_1)        | 6     |
u3/clk10:Q                         | NONE                      | 42    |
u2/clk1k:Q                         | NONE                      | 15    |
u2/button(u2/button1:O)            | NONE(*)(u2/ss1_2)         | 18    |
u0/clk1m:Q                         | BUFG                      | 102   |
u1/u0/clk_12MHz:Q                  | NONE                      | 4     |
u1/u3/PreCLK(u1/u3/PreCLK1:O)      | NONE(*)(u1/u3/Count11_6)  | 12    |
u1/u3/FullSpkS:Q                   | NONE                      | 1     |
u1/u2/_n0003(u1/u2/_n00031:O)      | NONE(*)(u1/u2/Tone_5)     | 11    |
u1/u1/_n0002(u1/u1/_n0002:O)       | NONE(*)(u1/u1/ToneIndex_3)| 4     |
u1/u0/clk_8Hz:Q                    | NONE                      | 8     |
-----------------------------------+---------------------------+-------+
(*) These 15 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 22.306ns (Maximum Frequency: 44.831MHz)
   Minimum input arrival time before clock: 11.533ns
   Maximum output required time after clock: 11.939ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'u4/clk1k:Q'
  Clock period: 22.306ns (frequency: 44.831MHz)
  Total number of paths / destination ports: 2067 / 136
-------------------------------------------------------------------------
Delay:               11.153ns (Levels of Logic = 5)
  Source:            u4/u3/c_2 (FF)
  Destination:       u4/u1/data_1 (FF)
  Source Clock:      u4/clk1k:Q rising
  Destination Clock: u4/clk1k:Q falling

  Data Path: u4/u3/c_2 to u4/u1/data_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             17   0.992   2.850  u4/u3/c_2 (u4/u3/c_2)
     LUT2:I1->O            8   0.468   2.050  u4/Ker201 (u4/N201)
     LUT4_L:I0->LO         1   0.468   0.100  u4/u1/_n0011<1>15 (CHOICE4582)
     LUT4:I3->O            1   0.468   0.920  u4/u1/_n0011<1>28 (CHOICE4586)
     MUXF5:S->O            1   0.725   0.920  u4/u1/_n0011<1>50_SW01 (N3313)
     LUT4_L:I0->LO         1   0.468   0.000  u4/u1/_n0011<1>67 (u4/u1/_n0011<1>)
     FDE_1:D                   0.724          u4/u1/data_1
    ----------------------------------------
    Total                     11.153ns (4.313ns logic, 6.840ns route)
                                       (38.7% logic, 61.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 14.156ns (frequency: 70.641MHz)
  Total number of paths / destination ports: 70748 / 412
-------------------------------------------------------------------------
Delay:               14.156ns (Levels of Logic = 5)
  Source:            u4/clk1k (FF)
  Destination:       u4/u5/u1/cnt6_3 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: u4/clk1k to u4/u5/u1/cnt6_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             1   0.992   0.920  u4/clk1k (u4/clk1k1)
     BUFG:I->O            97   0.500   4.925  u4/clk1k_BUFG (u4/clk1k)
     LUT3:I2->O            3   0.468   1.320  u4/reg_tclk1 (u4/reg_tclk)
     LUT4_D:I1->LO         1   0.468   0.100  u4/u5/u1/Ker0 (N3466)
     LUT4:I0->O            3   0.468   1.320  u4/u5/u1/Ker2 (u4/u5/u1/N2)
     LUT3:I0->O            4   0.468   1.520  u4/u5/u1/_n00681 (u4/u5/u1/_n0068)
     FDE:CE                    0.687          u4/u5/u1/cnt4_0
    ----------------------------------------
    Total                     14.156ns (4.051ns logic, 10.105ns route)
                                       (28.6% logic, 71.4% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'u4/u4/u0/sclkb:Q'
  Clock period: 8.167ns (frequency: 122.444MHz)
  Total number of paths / destination ports: 133 / 12
-------------------------------------------------------------------------
Delay:               8.167ns (Levels of Logic = 3)
  Source:            u4/u4/u0/c1_3 (FF)
  Destination:       u4/u4/u0/d1_0 (FF)
  Source Clock:      u4/u4/u0/sclkb:Q rising
  Destination Clock: u4/u4/u0/sclkb:Q rising

  Data Path: u4/u4/u0/c1_3 to u4/u4/u0/d1_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            4   0.992   1.520  u4/u4/u0/c1_3 (u4/u4/u0/c1_3)
     LUT4:I0->O            3   0.468   1.320  u4/u4/u0/Ker71 (u4/u4/u0/N7)
     MUXF5:S->O            7   0.725   1.950  u4/u4/u0/_n0039 (u4/u4/u0/_n0039)
     LUT3:I2->O            1   0.468   0.000  u4/u4/u0/_n0021<1>1 (u4/u4/u0/_n0021<1>)
     FDC:D                     0.724          u4/u4/u0/d1_1
    ----------------------------------------
    Total                      8.167ns (3.377ns logic, 4.790ns route)
                                       (41.3% logic, 58.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'u4/clk1:Q'
  Clock period: 6.405ns (frequency: 156.128MHz)
  Total number of paths / destination ports: 44 / 13
-------------------------------------------------------------------------
Delay:               6.405ns (Levels of Logic = 2)
  Source:            u4/u4/u0/c_0 (FF)
  Destination:       u4/u4/u0/sclka (FF)
  Source Clock:      u4/clk1:Q rising
  Destination Clock: u4/clk1:Q rising

  Data Path: u4/u4/u0/c_0 to u4/u4/u0/sclka
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              7   0.992   1.950  u4/u4/u0/c_0 (u4/u4/u0/c_0)
     LUT4:I1->O            1   0.468   0.920  u4/u4/u0/_n00131 (u4/u4/u0/N8)
     LUT2:I1->O            1   0.468   0.920  u4/u4/u0/_n00132 (u4/u4/u0/_n0013)
     FDE:CE                    0.687          u4/u4/u0/sclka
    ----------------------------------------
    Total                      6.405ns (2.615ns logic, 3.790ns route)
                                       (40.8% logic, 59.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'u4/u4/u0/sclka:Q'
  Clock period: 6.405ns (frequency: 156.128MHz)
  Total number of paths / destination ports: 43 / 12
-------------------------------------------------------------------------
Delay:               6.405ns (Levels of Logic = 2)
  Source:            u4/u4/u0/c0_0 (FF)
  Destination:       u4/u4/u0/sclkb (FF)
  Source Clock:      u4/u4/u0/sclka:Q rising
  Destination Clock: u4/u4/u0/sclka:Q rising

  Data Path: u4/u4/u0/c0_0 to u4/u4/u0/sclkb
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              7   0.992   1.950  u4/u4/u0/c0_0 (u4/u4/u0/c0_0)
     LUT4:I1->O            1   0.468   0.920  u4/u4/u0/_n00151 (u4/u4/u0/N20)
     LUT2:I1->O            1   0.468   0.920  u4/u4/u0/_n00152 (u4/u4/u0/_n0015)
     FDE:CE                    0.687          u4/u4/u0/sclkb
    ----------------------------------------
    Total                      6.405ns (2.615ns logic, 3.790ns route)
                                       (40.8% logic, 59.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'u2/clk1:Q'
  Clock period: 11.231ns (frequency: 89.039MHz)
  Total number of paths / destination ports: 249 / 24
-------------------------------------------------------------------------
Delay:               11.231ns (Levels of Logic = 4)
  Source:            u2/s0_0 (FF)
  Destination:       u2/s3_3 (FF)
  Source Clock:      u2/clk1:Q rising
  Destination Clock: u2/clk1:Q rising

  Data Path: u2/s0_0 to u2/s3_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               7   0.992   1.950  u2/s0_0 (u2/s0_0)
     LUT4:I0->O            8   0.468   2.050  u2/_n00531 (u2/_n0085<2>)
     LUT4:I2->O            7   0.468   1.950  u2/Ker311 (u2/N31)
     LUT3:I2->O            1   0.468   0.920  u2/Ker341 (u2/N34)
     LUT4:I0->O            1   0.468   0.920  u2/_n0032<3>57 (CHOICE4308)
     FDS:S                     0.577          u2/s3_3
    ----------------------------------------
    Total                     11.231ns (3.441ns logic, 7.790ns route)
                                       (30.6% logic, 69.4% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'u4/reg_clk1k2:O'
  Clock period: 14.013ns (frequency: 71.362MHz)
  Total number of paths / destination ports: 18051 / 191
-------------------------------------------------------------------------
Delay:               14.013ns (Levels of Logic = 10)
  Source:            u4/u7/reg_4 (FF)
  Destination:       u4/u7/d5_3 (FF)
  Source Clock:      u4/reg_clk1k2:O rising
  Destination Clock: u4/reg_clk1k2:O rising

  Data Path: u4/u7/reg_4 to u4/u7/d5_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              7   0.992   1.950  u4/u7/reg_4 (u4/u7/reg_4)
     LUT4:I0->O            1   0.468   0.000  u4/u7/norlut5 (u4/u7/N14)
     MUXCY:S->O            1   0.51