demo_all.syr

总体演示程序DEMO_FPGA.rar

    Found 1-bit register for signal <clk1k>.
    Found 16-bit up counter for signal <cnt>.
    Found 10-bit up counter for signal <cnt0>.
    Summary:
	inferred   2 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   4 Comparator(s).
Unit <Top_FPGA_demo> synthesized.


Synthesizing Unit <reject1>.
    Related source file is "E:/DEMO_FPGA/reject.vhd".
WARNING:Xst:1780 - Signal <div_mode> is never used or assigned.
    Found 19-bit 4-to-1 multiplexer for signal <$n0011>.
    Found 2-bit comparator less for signal <$n0013> created at line 39.
    Found 3-bit comparator less for signal <$n0014> created at line 87.
    Found 2-bit comparator less for signal <$n0016> created at line 28.
    Found 19-bit comparator less for signal <$n0017> created at line 64.
    Found 19-bit comparator less for signal <$n0018> created at line 64.
    Found 23-bit comparator less for signal <$n0019> created at line 75.
    Found 19-bit adder for signal <$n0036> created at line 63.
    Found 19-bit addsub for signal <$n0037>.
    Found 3-bit adder for signal <$n0039> created at line 98.
    Found 23-bit adder for signal <$n0040> created at line 74.
    Found 3-bit comparator less for signal <$n0042> created at line 98.
    Found 19-bit comparator greater for signal <$n0049> created at line 49.
    Found 19-bit comparator less for signal <$n0050> created at line 53.
    Found 1-bit xor2 for signal <button>.
    Found 1-bit register for signal <clk10>.
    Found 1-bit register for signal <clk100>.
    Found 19-bit up counter for signal <cnt>.
    Found 23-bit up counter for signal <cnt0>.
    Found 3-bit register for signal <cnt1>.
    Found 19-bit register for signal <del>.
    Found 8-bit register for signal <pout1>.
    Found 8-bit register for signal <q>.
    Found 8-bit register for signal <q1>.
    Found 2-bit up counter for signal <t>.
    Found 2-bit up counter for signal <t0>.
    Found 3-bit up counter for signal <t1>.
    Summary:
	inferred   5 Counter(s).
	inferred  48 D-type flip-flop(s).
	inferred   4 Adder/Subtractor(s).
	inferred   9 Comparator(s).
	inferred  19 Multiplexer(s).
Unit <reject1> synthesized.


Synthesizing Unit <demo2>.
    Related source file is "E:/DEMO_FPGA/demo2.vhd".
    Found 16x8-bit ROM for signal <led>.
    Found 4-bit register for signal <led_shift>.
    Found 7-bit comparator less for signal <$n0025> created at line 53.
    Found 4-bit 4-to-1 multiplexer for signal <$n0028>.
    Found 16-bit comparator less for signal <$n0029> created at line 42.
    Found 4-bit 4-to-1 multiplexer for signal <$n0030>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0031>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0032>.
    Found 2-bit comparator less for signal <$n0035> created at line 32.
    Found 1-of-4 decoder for signal <$n0037>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0038>.
    Found 7-bit adder for signal <$n0039> created at line 52.
    Found 16-bit adder for signal <$n0040> created at line 41.
    Found 2-bit adder for signal <$n0041> created at line 131.
    Found 4-bit adder for signal <$n0042> created at line 86.
    Found 4-bit adder for signal <$n0043> created at line 84.
    Found 4-bit adder for signal <$n0044> created at line 82.
    Found 4-bit adder for signal <$n0045> created at line 80.
    Found 2-bit adder for signal <$n0046> created at line 65.
    Found 4-bit 4-to-1 multiplexer for signal <$n0049>.
    Found 2-bit comparator less for signal <$n0052> created at line 65.
    Found 16-bit comparator less for signal <$n0062> created at line 42.
    Found 7-bit comparator less for signal <$n0063> created at line 53.
    Found 1-bit xor2 for signal <button>.
    Found 2-bit up counter for signal <c>.
    Found 1-bit register for signal <clk1>.
    Found 1-bit register for signal <clk1k>.
    Found 16-bit up counter for signal <cnt>.
    Found 7-bit up counter for signal <cnt0>.
    Found 4-bit register for signal <data>.
    Found 4-bit register for signal <s0>.
    Found 4-bit register for signal <s1>.
    Found 4-bit register for signal <s2>.
    Found 4-bit register for signal <s3>.
    Found 2-bit register for signal <s_button>.
    Found 4-bit up counter for signal <ss0>.
    Found 4-bit up counter for signal <ss1>.
    Found 4-bit up counter for signal <ss2>.
    Found 4-bit up counter for signal <ss3>.
    Found 2-bit up counter for signal <t>.
    Summary:
	inferred   1 ROM(s).
	inferred   8 Counter(s).
	inferred  28 D-type flip-flop(s).
	inferred   8 Adder/Subtractor(s).
	inferred   6 Comparator(s).
	inferred  24 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <demo2> synthesized.


Synthesizing Unit <Songer>.
    Related source file is "E:/DEMO_FPGA/songer.vhd".
Unit <Songer> synthesized.


Synthesizing Unit <demo1>.
    Related source file is "E:/DEMO_FPGA/demo1.vhd".
WARNING:Xst:1780 - Signal <addr> is never used or assigned.
WARNING:Xst:1780 - Signal <din> is never used or assigned.
WARNING:Xst:1780 - Signal <we> is never used or assigned.
WARNING:Xst:1780 - Signal <dout> is never used or assigned.
    Found 12-bit 4-to-1 multiplexer for signal <$n0028>.
    Found 6-bit comparator less for signal <$n0035> created at line 27.
    Found 12-bit 4-to-1 multiplexer for signal <$n0038>.
    Found 12-bit 4-to-1 multiplexer for signal <$n0039>.
    Found 12-bit 4-to-1 multiplexer for signal <$n0040>.
    Found 12-bit 4-to-1 multiplexer for signal <$n0041>.
    Found 12-bit 4-to-1 multiplexer for signal <$n0042>.
    Found 11-bit 4-to-1 multiplexer for signal <$n0043>.
    Found 11-bit 4-to-1 multiplexer for signal <$n0044>.
    Found 12-bit adder for signal <$n0045> created at line 40.
    Found 12-bit adder for signal <$n0046> created at line 52.
    Found 12-bit adder for signal <$n0047> created at line 64.
    Found 12-bit adder for signal <$n0048> created at line 76.
    Found 12-bit adder for signal <$n0049> created at line 88.
    Found 12-bit adder for signal <$n0050> created at line 100.
    Found 11-bit adder for signal <$n0051> created at line 112.
    Found 11-bit adder for signal <$n0052> created at line 124.
    Found 6-bit adder for signal <$n0053> created at line 27.
    Found 12-bit comparator less for signal <$n0054> created at line 41.
    Found 12-bit comparator less for signal <$n0055> created at line 53.
    Found 12-bit comparator less for signal <$n0056> created at line 65.
    Found 12-bit comparator less for signal <$n0057> created at line 77.
    Found 12-bit comparator less for signal <$n0058> created at line 89.
    Found 12-bit comparator less for signal <$n0059> created at line 65.
    Found 12-bit comparator less for signal <$n0060> created at line 101.
    Found 11-bit comparator less for signal <$n0061> created at line 113.
    Found 11-bit comparator less for signal <$n0062> created at line 125.
    Found 6-bit comparator less for signal <$n0063> created at line 28.
    Found 12-bit comparator less for signal <$n0064> created at line 41.
    Found 12-bit comparator less for signal <$n0065> created at line 53.
    Found 12-bit comparator less for signal <$n0066> created at line 77.
    Found 12-bit comparator less for signal <$n0067> created at line 89.
    Found 12-bit comparator less for signal <$n0068> created at line 101.
    Found 11-bit comparator less for signal <$n0069> created at line 113.
    Found 11-bit comparator less for signal <$n0070> created at line 125.
    Found 1-bit register for signal <aa>.
    Found 1-bit register for signal <bb>.
    Found 6-bit up counter for signal <c0>.
    Found 12-bit register for signal <c1>.
    Found 12-bit register for signal <c2>.
    Found 12-bit register for signal <c3>.
    Found 12-bit register for signal <c4>.
    Found 12-bit register for signal <c5>.
    Found 11-bit register for signal <c6>.
    Found 11-bit register for signal <c7>.
    Found 1-bit register for signal <cc>.
    Found 1-bit register for signal <clk1m>.
    Found 12-bit register for signal <ct>.
    Found 1-bit register for signal <dd>.
    Found 1-bit register for signal <ee>.
    Found 1-bit register for signal <ff>.
    Found 1-bit register for signal <gg>.
    Found 1-bit register for signal <hh>.
    Summary:
	inferred   1 Counter(s).
	inferred 103 D-type flip-flop(s).
	inferred   9 Adder/Subtractor(s).
	inferred  18 Comparator(s).
	inferred  94 Multiplexer(s).
Unit <demo1> synthesized.


Synthesizing Unit <demo_all>.
    Related source file is "E:/DEMO_FPGA/demo_all.vhd".
WARNING:Xst:646 - Signal <css> is assigned but never used.
WARNING:Xst:1780 - Signal <clk1> is never used or assigned.
WARNING:Xst:1780 - Signal <clk2> is never used or assigned.
WARNING:Xst:1780 - Signal <clk3> is never used or assigned.
WARNING:Xst:1780 - Signal <clk4> is never used or assigned.
WARNING:Xst:646 - Signal <csss> is assigned but never used.
WARNING:Xst:646 - Signal <shift3> is assigned but never used.
WARNING:Xst:737 - Found 1-bit latch for signal <istepa>.
WARNING:Xst:737 - Found 1-bit latch for signal <istepb>.
WARNING:Xst:737 - Found 8-bit latch for signal <button1>.
WARNING:Xst:737 - Found 1-bit latch for signal <ienter>.
WARNING:Xst:737 - Found 4-bit latch for signal <button3a>.
WARNING:Xst:737 - Found 1-bit latch for signal <ireset>.
WARNING:Xst:737 - Found 8-bit latch for signal <led>.
WARNING:Xst:737 - Found 2-bit latch for signal <cs>.
WARNING:Xst:737 - Found 1-bit latch for signal <but>.
WARNING:Xst:737 - Found 1-bit latch for signal <button2>.
WARNING:Xst:737 - Found 1-bit latch for signal <button3>.
WARNING:Xst:737 - Found 3-bit latch for signal <mode1>.
WARNING:Xst:737 - Found 4-bit latch for signal <led_shift>.
WARNING:Xst:737 - Found 1-bit latch for signal <tone>.
WARNING:Xst:737 - Found 1-bit latch for signal <but1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0012>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0014>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0016>.
    Summary:
	inferred   8 Multiplexer(s).
Unit <demo_all> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
INFO:Xst:1651 - Address input of ROM <Mrom_led> in block <demo2> is tied to register <data> in block <demo2>.
INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM.
Advanced multiplier inference ...
INFO:Xst:1784 - HDL ADVISOR - Multiplier(s) is(are) identified in your design. You can improve the performance of your multiplier by using the pipeline feature available with mult_style attribute.
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <FSM_3> on signal <current_state[1:8]> with speed1 encoding.
--------------------------------
 State              | Encoding
--------------------------------
 set_dlnf           | 10000000
 clear_lcd          | 01000000
 set_cursor         | 00100000
 set_location3      | 00000001
 write_data2        | 00010000
 set_dcb            | 00001000
 set_location       | 00000100
 write_data         | 00000010
 write_data3        | unreached
 set_location2      | unreached
 set_cgram_location | unreached
 write_cgram        | unreached
--------------------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <FSM_2> on signal <current_state[1:4]> with gray encoding.
-------------------
 State | Encoding
-------------------
 st0   | 0000
 st1   | 0010
 st2   | 0110
 st3   | 0011
 st4   | 0111
 st5   | 0001
 st6   | 0101
 st7   | 0100
 st8   | 1100
 st9   | 1101
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <FSM_1> on signal <current_state2[1:5]> with speed1 encoding.
-------------------
 State | Encoding
-------------------
 st0   | 10000
 st1   | 01000
 st2   | 00100
 st3   | 00010
 st4   | 00001
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <current_state1[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 st0   | 00
 st1   | 01
 st2   | 10
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics