mem_inform.vhd

来自「总体演示程序DEMO_FPGA.rar」· VHDL 代码 · 共 48 行

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-- Company: 
-- Engineer:
--
-- Create Date:    22:30:58 03/23/05
-- Design Name:    
-- Module Name:    page_information - data
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity page_information is
	port (
	addr: IN std_logic_VECTOR(9 downto 0);
	clk: IN std_logic;
	dout: OUT std_logic_VECTOR(7 downto 0));
end page_information;

architecture data of page_information is
component mem_infor
	port (
	addr: IN std_logic_VECTOR(9 downto 0);
	clk: IN std_logic;
	dout: OUT std_logic_VECTOR(7 downto 0));
end component;

begin
U0 : mem_infor
		port map (
			addr => addr,
			clk => clk,
			dout => dout);

end data;