digital_voltmeter.syr

总体演示程序DEMO_FPGA.rar

# Counters                         : 1
 3-bit up counter                  : 1
# Registers                        : 28
 1-bit register                    : 17
 16-bit register                   : 2
 17-bit register                   : 1
 2-bit register                    : 1
 4-bit register                    : 5
 5-bit register                    : 1
 8-bit register                    : 1
# Comparators                      : 5
 17-bit comparator greater         : 4
 3-bit comparator less             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Register <current_state_0> equivalent to <clk_tlc549> has been removed
WARNING:Xst:1291 - FF/Latch <reg_din_0> is unconnected in block <digital_voltmeter>.
WARNING:Xst:1291 - FF/Latch <reg_0> is unconnected in block <digital_voltmeter>.

Optimizing unit <digital_voltmeter> ...
Loading device for application Rf_Device from file '2s100e.nph' in environment E:/Program/EDA/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block digital_voltmeter, actual ratio is 11.
FlipFlop clk_tlc549 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : digital_voltmeter.ngr
Top Level Output File Name         : digital_voltmeter
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 18

Macro Statistics :
# Registers                        : 22
#      1-bit register              : 10
#      16-bit register             : 2
#      17-bit register             : 1
#      2-bit register              : 1
#      3-bit register              : 1
#      4-bit register              : 5
#      5-bit register              : 1
#      8-bit register              : 1
# Adders/Subtractors               : 5
#      17-bit subtractor           : 1
#      4-bit adder                 : 4
# Multipliers                      : 1
#      8x8-bit multiplier          : 1
# Comparators                      : 5
#      17-bit comparator greater   : 4
#      3-bit comparator less       : 1

Cell Usage :
# BELS                             : 365
#      GND                         : 1
#      INV                         : 17
#      LUT1                        : 6
#      LUT1_L                      : 15
#      LUT2                        : 35
#      LUT2_D                      : 2
#      LUT2_L                      : 37
#      LUT3                        : 8
#      LUT3_L                      : 10
#      LUT4                        : 59
#      LUT4_D                      : 1
#      LUT4_L                      : 30
#      MUXCY                       : 73
#      MUXF5                       : 20
#      VCC                         : 1
#      XORCY                       : 50
# FlipFlops/Latches                : 102
#      FD                          : 20
#      FDE                         : 47
#      FDR                         : 3
#      FDRE                        : 3
#      FDS                         : 29
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 17
#      IBUF                        : 1
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100epq208-6 

 Number of Slices:                     122  out of   1200    10%  
 Number of Slice Flip Flops:           102  out of   2400     4%  
 Number of 4 input LUTs:               203  out of   2400     8%  
 Number of bonded IOBs:                 18  out of    146    12%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk1k                              | BUFGP                  | 102   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 13.008ns (Maximum Frequency: 76.876MHz)
   Minimum input arrival time before clock: 2.441ns
   Maximum output required time after clock: 10.254ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk1k'
  Clock period: 13.008ns (frequency: 76.876MHz)
  Total number of paths / destination ports: 15812 / 184
-------------------------------------------------------------------------
Delay:               13.008ns (Levels of Logic = 9)
  Source:            reg_4 (FF)
  Destination:       reg_15 (FF)
  Source Clock:      clk1k rising
  Destination Clock: clk1k rising

  Data Path: reg_4 to reg_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              6   0.992   1.850  reg_4 (reg_4)
     LUT4_L:I0->LO         1   0.468   0.000  norlut5 (N13)
     MUXCY:S->O            1   0.515   0.000  norcy_rn_4 (nor_cyo5)
     MUXCY:CI->O           1   0.058   0.000  Andcy_rn_0 (And_cyo1)
     MUXCY:CI->O           1   0.058   0.000  norcy_rn_5 (nor_cyo6)
     MUXCY:CI->O           1   0.058   0.000  Andcy_rn_1 (And_cyo2)
     MUXCY:CI->O          26   0.058   3.150  norcy_rn_6 (nor_cyo7)
     LUT3_L:I0->LO         1   0.468   0.100  Ker11_SW1 (N427)
     LUT4:I3->O           16   0.468   2.800  Ker11 (N1110)
     LUT4:I2->O            1   0.468   0.920  _n0027<10>_SW0 (N77)
     FDS:S                     0.577          reg_10
    ----------------------------------------
    Total                     13.008ns (4.188ns logic, 8.820ns route)
                                       (32.2% logic, 67.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk1k'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              2.441ns (Levels of Logic = 1)
  Source:            din (PAD)
  Destination:       datain_0 (FF)
  Destination Clock: clk1k rising

  Data Path: din to datain_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.797   0.920  din_IBUF (din_IBUF)
     FDE:D                     0.724          datain_0
    ----------------------------------------
    Total                      2.441ns (1.521ns logic, 0.920ns route)
                                       (62.3% logic, 37.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk1k'
  Total number of paths / destination ports: 77 / 15
-------------------------------------------------------------------------
Offset:              10.254ns (Levels of Logic = 3)
  Source:            dout_2 (FF)
  Destination:       dout_led<7> (PAD)
  Source Clock:      clk1k rising

  Data Path: dout_2 to dout_led<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q             17   0.992   2.850  dout_2 (dout_2)
     LUT4:I1->O            1   0.468   0.000  dout_led<6>1_F (N109)
     MUXF5:I0->O           1   0.422   0.920  dout_led<6>1 (dout_led_6_OBUF)
     OBUF:I->O                 4.602          dout_led_6_OBUF (dout_led<6>)
    ----------------------------------------
    Total                     10.254ns (6.484ns logic, 3.770ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
CPU : 20.00 / 20.87 s | Elapsed : 20.00 / 20.00 s
 
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Total memory usage is 89508 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    3 (   0 filtered)