digital_voltmeter.syr

总体演示程序DEMO_FPGA.rar

Release 7.1.01i - xst H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: digital_voltmeter.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "digital_voltmeter.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "digital_voltmeter"
Output Format                      : NGC
Target Device                      : xc2s100e-6-pq208

---- Source Options
Top Module Name                    : digital_voltmeter
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : digital_voltmeter.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/DEMO_FPGA/DEMO_ADC.vhd" in Library work.
Entity <digital_voltmeter> compiled.
Entity <digital_voltmeter> (Architecture <adc>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <digital_voltmeter> (Architecture <adc>).
WARNING:Xst:819 - "E:/DEMO_FPGA/DEMO_ADC.vhd" line 146: The following signals are missing in the process sensitivity list:
   reg_datain.
INFO:Xst:1304 - Contents of register <cs_tlc549> in unit <digital_voltmeter> never changes during circuit operation. The register is replaced by logic.
Entity <digital_voltmeter> analyzed. Unit <digital_voltmeter> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <digital_voltmeter>.
    Related source file is "E:/DEMO_FPGA/DEMO_ADC.vhd".
    Found finite state machine <FSM_0> for signal <current_state1>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 7                                              |
    | Inputs             | 4                                              |
    | Outputs            | 3                                              |
    | Clock              | clk1k (rising_edge)                            |
    | Power Up State     | st0                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <current_state2>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 5                                              |
    | Inputs             | 0                                              |
    | Outputs            | 5                                              |
    | Clock              | clk1k (rising_edge)                            |
    | Power Up State     | st0                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <clk_tlc549>.
    Found 4-bit register for signal <shift>.
    Found 2-bit register for signal <cs_led>.
    Found 17-bit comparator greater for signal <$n0006> created at line 94.
    Found 17-bit comparator greater for signal <$n0007> created at line 94.
    Found 17-bit comparator greater for signal <$n0008> created at line 95.
    Found 17-bit comparator greater for signal <$n0009> created at line 96.
    Found 8x8-bit multiplier for signal <$n0028> created at line 73.
    Found 17-bit subtractor for signal <$n0029> created at line 94.
    Found 4-bit adder for signal <$n0031> created at line 94.
    Found 4-bit adder for signal <$n0032> created at line 95.
    Found 4-bit adder for signal <$n0033> created at line 96.
    Found 4-bit adder for signal <$n0034> created at line 97.
    Found 3-bit comparator less for signal <$n0045> created at line 71.
    Found 3-bit up counter for signal <cnt>.
    Found 1-bit register for signal <current_state<0>>.
    Found 4-bit register for signal <d1>.
    Found 4-bit register for signal <d2>.
    Found 4-bit register for signal <d3>.
    Found 4-bit register for signal <d4>.
    Found 8-bit register for signal <datain>.
    Found 5-bit register for signal <dout>.
    Found 17-bit register for signal <reg>.
    Found 8-bit register for signal <reg_datain>.
    Found 16-bit register for signal <reg_din>.
    Found 16-bit register for signal <reg_dout>.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  94 D-type flip-flop(s).
	inferred   5 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
	inferred   5 Comparator(s).
Unit <digital_voltmeter> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
INFO:Xst:1784 - HDL ADVISOR - Multiplier(s) is(are) identified in your design. You can improve the performance of your multiplier by using the pipeline feature available with mult_style attribute.
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <FSM_1> on signal <current_state2[1:5]> with speed1 encoding.
-------------------
 State | Encoding
-------------------
 st0   | 10000
 st1   | 01000
 st2   | 00100
 st3   | 00010
 st4   | 00001
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <current_state1[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 st0   | 00
 st1   | 01
 st2   | 10
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 2
# Multipliers                      : 1
 8x8-bit multiplier                : 1
# Adders/Subtractors               : 5
 17-bit subtractor                 : 1
 4-bit adder                       : 4