hdpdeps.ref

总体演示程序DEMO_FPGA.rar

V2 108
FL E:/DEMO_FPGA/page3.vhd 2005/03/25.06:47:48 H.38
EN work/PAGE3 1112541520           FL E:/DEMO_FPGA/page3.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/PAGE3/BEHAVIORAL 1112541521 FL E:/DEMO_FPGA/page3.vhd EN work/PAGE3 1112541520
FL E:/DEMO_FPGA/demo2.vhd 2005/03/25.09:27:57 H.38
EN work/DEMO2 1112541534           FL E:/DEMO_FPGA/demo2.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/DEMO2/BEHAVIORAL 1112541535 FL E:/DEMO_FPGA/demo2.vhd EN work/DEMO2 1112541534
FL E:/DEMO_FPGA/page_dclk.vhd 2005/03/25.03:22:46 H.38
EN work/PAGE1 1112541500           FL E:/DEMO_FPGA/page_dclk.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/PAGE1/DIGITAL_CLOCK 1112541501 FL E:/DEMO_FPGA/page_dclk.vhd EN work/PAGE1 1112541500
FL E:/DEMO_FPGA/page_step.vhd 2005/03/25.02:26:55 H.38
EN work/PAGE_STEP 1112541510       FL E:/DEMO_FPGA/page_step.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/PAGE_STEP/BEHAVIORAL 1112541511 FL E:/DEMO_FPGA/page_step.vhd EN work/PAGE_STEP 1112541510
FL E:/DEMO_FPGA/DEMO_ADC.vhd 2005/03/25.06:09:22 H.38
EN work/DIGITAL_VOLTMETER 1112541518 FL E:/DEMO_FPGA/DEMO_ADC.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/DIGITAL_VOLTMETER/ADC 1112541519 FL E:/DEMO_FPGA/DEMO_ADC.vhd \
      EN work/DIGITAL_VOLTMETER 1112541518
FL E:/DEMO_FPGA/mem_inform.vhd 2005/03/24.14:49:55 H.38
EN work/PAGE_INFORMATION 1112541504 FL E:/DEMO_FPGA/mem_inform.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/PAGE_INFORMATION/DATA 1112541505 FL E:/DEMO_FPGA/mem_inform.vhd \
      EN work/PAGE_INFORMATION 1112541504 CP MEM_INFOR
FL E:/DEMO_FPGA/top_mode_cymometer.vhd 2005/03/25.04:08:45 H.38
EN work/TOP_MODE_CYMOMETER 1112541514 FL E:/DEMO_FPGA/top_mode_cymometer.vhd \
      PB ieee/STD_LOGIC_1164 1106404628 PB ieee/STD_LOGIC_ARITH 1106404630 \
      PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/TOP_MODE_CYMOMETER/BEHAVIORAL 1112541515 FL E:/DEMO_FPGA/top_mode_cymometer.vhd \
      EN work/TOP_MODE_CYMOMETER 1112541514 CP PAGE4 CP MODE_CYMOMETER
FL E:/DEMO_FPGA/mode_cymometer.vhd 2005/03/25.04:51:51 H.38
EN work/MODE_CYMOMETER 1112541496  FL E:/DEMO_FPGA/mode_cymometer.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/MODE_CYMOMETER/BEHAVIORAL 1112541497 FL E:/DEMO_FPGA/mode_cymometer.vhd \
      EN work/MODE_CYMOMETER 1112541496
FL E:/DEMO_FPGA/page4.vhd 2005/03/25.04:23:28 H.38
EN work/PAGE4 1112541494           FL E:/DEMO_FPGA/page4.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/PAGE4/BEHAVIORAL 1112541495 FL E:/DEMO_FPGA/page4.vhd EN work/PAGE4 1112541494
FL E:/DEMO_FPGA/electronic_organ.vhd 2005/03/25.06:02:12 H.38
EN work/ELECTRONIC_ORGAN 1112541516 FL E:/DEMO_FPGA/electronic_organ.vhd \
      PB ieee/STD_LOGIC_1164 1106404628 PB ieee/STD_LOGIC_ARITH 1106404630 \
      PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/ELECTRONIC_ORGAN/BEHAVIORAL 1112541517 FL E:/DEMO_FPGA/electronic_organ.vhd \
      EN work/ELECTRONIC_ORGAN 1112541516
FL E:/DEMO_FPGA/keyboards.vhd 2005/03/24.23:29:34 H.38
EN work/KEYBOARDS 1112541508       FL E:/DEMO_FPGA/keyboards.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/KEYBOARDS/BEHAVIORAL 1112541509 FL E:/DEMO_FPGA/keyboards.vhd EN work/KEYBOARDS 1112541508 \
      CP BUTTON1
FL E:/DEMO_FPGA/tonetaba.vhd 2005/03/25.09:27:58 H.38
EN work/TONETABA 1112541526        FL E:/DEMO_FPGA/tonetaba.vhd PB ieee/STD_LOGIC_1164 1106404628
AR work/TONETABA/ONE 1112541527    FL E:/DEMO_FPGA/tonetaba.vhd EN work/TONETABA 1112541526
FL E:/DEMO_FPGA/mode_clk.vhd 2005/03/25.01:23:38 H.38
EN work/MODE_CLK 1112541512        FL E:/DEMO_FPGA/mode_clk.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/MODE_CLK/BEHAVIORAL 1112541513 FL E:/DEMO_FPGA/mode_clk.vhd EN work/MODE_CLK 1112541512 \
      CP DIGITAL_CLK    CP PAGE1
FL E:/DEMO_FPGA/reject.vhd 2005/03/25.09:27:57 H.38
EN work/REJECT1 1112541536         FL E:/DEMO_FPGA/reject.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/REJECT1/BEHAVIORAL 1112541537 FL E:/DEMO_FPGA/reject.vhd EN work/REJECT1 1112541536
FL E:/DEMO_FPGA/speakera.vhd 2005/03/25.09:27:56 H.38
EN work/SPEAKERA 1112541528        FL E:/DEMO_FPGA/speakera.vhd PB ieee/STD_LOGIC_1164 1106404628
AR work/SPEAKERA/ONE 1112541529    FL E:/DEMO_FPGA/speakera.vhd EN work/SPEAKERA 1112541528
FL E:/DEMO_FPGA/address_gen.vhd 2005/03/24.13:24:03 H.38
EN work/ADDRESS_GEN 1111641847     FL E:/DEMO_FPGA/address_gen.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/ADDRESS_GEN/PAGE_INFORMATION 1111641848 FL E:/DEMO_FPGA/address_gen.vhd \
      EN work/ADDRESS_GEN 1111641847
FL E:/DEMO_FPGA/demo_all.vhd 2005/04/03.23:01:40 H.38
EN work/DEMO_ALL 1112541540        FL E:/DEMO_FPGA/demo_all.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/DEMO_ALL/BEHAVIORAL 1112541541 FL E:/DEMO_FPGA/demo_all.vhd EN work/DEMO_ALL 1112541540 \
      CP DEMO1          CP SONGER         CP DEMO2          CP REJECT1 \
      CP TOP_FPGA_DEMO
FL E:/DEMO_FPGA/button1.vhd 2005/03/25.00:10:39 H.38
EN work/BUTTON1 1112541502         FL E:/DEMO_FPGA/button1.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/BUTTON1/KEYBOARDS 1112541503 FL E:/DEMO_FPGA/button1.vhd EN work/BUTTON1 1112541502
FL E:/DEMO_FPGA/12MHz_generator.vhd 2005/03/25.09:30:54 H.38
EN work/MHZ_GENERATOR 1112541522   FL E:/DEMO_FPGA/12MHz_generator.vhd \
      PB ieee/STD_LOGIC_1164 1106404628 PB ieee/STD_LOGIC_ARITH 1106404630 \
      PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/MHZ_GENERATOR/BEHAVIORAL 1112541523 FL E:/DEMO_FPGA/12MHz_generator.vhd \
      EN work/MHZ_GENERATOR 1112541522
FL E:/DEMO_FPGA/Top_FPGA_demo.vhd 2005/03/25.06:47:21 H.38
EN work/TOP_FPGA_DEMO 1112541538   FL E:/DEMO_FPGA/Top_FPGA_demo.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/TOP_FPGA_DEMO/BEHAVIORAL 1112541539 FL E:/DEMO_FPGA/Top_FPGA_demo.vhd \
      EN work/TOP_FPGA_DEMO 1112541538 CP PAGE_INFORMATION CP LCD CP KEYBOARDS \
      CP PAGE_STEP      CP MODE_CLK       CP TOP_MODE_CYMOMETER \
      CP ELECTRONIC_ORGAN CP DIGITAL_VOLTMETER CP PAGE3
FL E:/DEMO_FPGA/notetabs.vhd 2005/03/25.09:29:15 H.38
EN work/NOTETABS 1112541524        FL E:/DEMO_FPGA/notetabs.vhd PB ieee/STD_LOGIC_1164 1106404628
AR work/NOTETABS/ONE 1112541525    FL E:/DEMO_FPGA/notetabs.vhd EN work/NOTETABS 1112541524
FL E:/DEMO_FPGA/lcd_driver.vhd 2005/03/24.13:53:49 H.38
EN work/LCD 1112541506             FL E:/DEMO_FPGA/lcd_driver.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/LCD/DRIVER 1112541507      FL E:/DEMO_FPGA/lcd_driver.vhd EN work/LCD 1112541506
FL E:/DEMO_FPGA/df.vhd 2005/04/08.10:37:13 H.38
EN work/DIANZIQIN 1112927837       FL E:/DEMO_FPGA/df.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/DIANZIQIN/BEHAV 1112927838 FL E:/DEMO_FPGA/df.vhd EN work/DIANZIQIN 1112927837
FL E:/DEMO_FPGA/demo1.vhd 2005/03/25.09:27:57 H.38
EN work/DEMO1 1112541530           FL E:/DEMO_FPGA/demo1.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/DEMO1/BEHAVIORAL 1112541531 FL E:/DEMO_FPGA/demo1.vhd EN work/DEMO1 1112541530
FL E:/DEMO_FPGA/digital_clk.vhd 2005/03/25.03:25:58 H.38
EN work/DIGITAL_CLK 1112541498     FL E:/DEMO_FPGA/digital_clk.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/DIGITAL_CLK/BEHAVIORAL 1112541499 FL E:/DEMO_FPGA/digital_clk.vhd \
      EN work/DIGITAL_CLK 1112541498
FL E:/DEMO_FPGA/button2.vhd 2005/03/24.23:06:28 H.38
EN work/BUTTON2 1111678000         FL E:/DEMO_FPGA/button2.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/BUTTON2/BEHAVIORAL 1111678001 FL E:/DEMO_FPGA/button2.vhd EN work/BUTTON2 1111678000
FL E:/DEMO_FPGA/songer.vhd 2005/03/25.09:27:57 H.38
EN work/SONGER 1112541532          FL E:/DEMO_FPGA/songer.vhd PB ieee/STD_LOGIC_1164 1106404628
AR work/SONGER/ONE 1112541533      FL E:/DEMO_FPGA/songer.vhd EN work/SONGER 1112541532 \
      CP MHZ_GENERATOR  CP NOTETABS       CP TONETABA       CP SPEAKERA
FL E:/DEMO_FPGA/uart.vhd 2005/03/25.08:31:05 H.38
EN work/UART 1111710669            FL E:/DEMO_FPGA/uart.vhd PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/UART/BEHAVIORAL 1111710670 FL E:/DEMO_FPGA/uart.vhd EN work/UART 1111710669