top_fpga_demo.syr

总体演示程序DEMO_FPGA.rar

  Destination:       u5/u1/cnt6_3 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: clk1k to u5/u1/cnt6_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             1   0.992   0.920  clk1k (clk1k1)
     BUFG:I->O            97   0.500   4.925  clk1k_BUFG (clk1k)
     LUT3:I1->O            3   0.468   1.320  reg_tclk1 (reg_tclk)
     LUT4_D:I2->LO         1   0.468   0.100  u5/u1/Ker0 (N2245)
     LUT4:I0->O            3   0.468   1.320  u5/u1/Ker2 (u5/u1/N2)
     LUT3:I2->O            4   0.468   1.520  u5/u1/_n00681 (u5/u1/_n0068)
     FDE:CE                    0.687          u5/u1/cnt4_0
    ----------------------------------------
    Total                     14.156ns (4.051ns logic, 10.105ns route)
                                       (28.6% logic, 71.4% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk1k:Q'
  Clock period: 22.306ns (frequency: 44.831MHz)
  Total number of paths / destination ports: 2067 / 136
-------------------------------------------------------------------------
Delay:               11.153ns (Levels of Logic = 5)
  Source:            u3/c_2 (FF)
  Destination:       u1/data_1 (FF)
  Source Clock:      clk1k:Q rising
  Destination Clock: clk1k:Q falling

  Data Path: u3/c_2 to u1/data_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             17   0.992   2.850  u3/c_2 (u3/c_2)
     LUT2:I1->O            8   0.468   2.050  Ker201 (N201)
     LUT4_L:I0->LO         1   0.468   0.100  u1/_n0011<1>15 (CHOICE2822)
     LUT4:I1->O            1   0.468   0.920  u1/_n0011<1>28 (CHOICE2826)
     MUXF5:S->O            1   0.725   0.920  u1/_n0011<1>50_SW01 (N2144)
     LUT4_L:I1->LO         1   0.468   0.000  u1/_n0011<1>67 (u1/_n0011<1>)
     FDE_1:D                   0.724          u1/data_1
    ----------------------------------------
    Total                     11.153ns (4.313ns logic, 6.840ns route)
                                       (38.7% logic, 61.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'reg_clk1k2:O'
  Clock period: 14.013ns (frequency: 71.362MHz)
  Total number of paths / destination ports: 18075 / 199
-------------------------------------------------------------------------
Delay:               14.013ns (Levels of Logic = 10)
  Source:            u7/reg_4 (FF)
  Destination:       u7/d5_3 (FF)
  Source Clock:      reg_clk1k2:O rising
  Destination Clock: reg_clk1k2:O rising

  Data Path: u7/reg_4 to u7/d5_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              7   0.992   1.950  u7/reg_4 (u7/reg_4)
     LUT4:I0->O            1   0.468   0.000  u7/norlut5 (u7/N14)
     MUXCY:S->O            1   0.515   0.000  u7/norcy_rn_4 (u7/nor_cyo5)
     MUXCY:CI->O           1   0.058   0.000  u7/Andcy (u7/And_cyo)
     MUXCY:CI->O           1   0.058   0.000  u7/norcy_rn_5 (u7/nor_cyo6)
     MUXCY:CI->O           1   0.058   0.000  u7/Andcy_rn_0 (u7/And_cyo1)
     MUXCY:CI->O          24   0.058   3.100  u7/norcy_rn_6 (u7/nor_cyo7)
     LUT3:I1->O            5   0.468   1.720  u7/Ker211 (u7/N211)
     LUT3:I2->O            4   0.468   1.520  u7/Ker81 (u7/N81)
     LUT4:I1->O            1   0.468   0.920  u7/_n0028<3>_SW0 (N1173)
     LUT4:I3->O            1   0.468   0.000  u7/_n0028<3> (u7/_n0028<3>)
     FD:D                      0.724          u7/d5_3
    ----------------------------------------
    Total                     14.013ns (4.803ns logic, 9.210ns route)
                                       (34.3% logic, 65.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk1:Q'
  Clock period: 6.405ns (frequency: 156.128MHz)
  Total number of paths / destination ports: 44 / 13
-------------------------------------------------------------------------
Delay:               6.405ns (Levels of Logic = 2)
  Source:            u4/u0/c_0 (FF)
  Destination:       u4/u0/sclka (FF)
  Source Clock:      clk1:Q rising
  Destination Clock: clk1:Q rising

  Data Path: u4/u0/c_0 to u4/u0/sclka
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              7   0.992   1.950  u4/u0/c_0 (u4/u0/c_0)
     LUT4:I1->O            1   0.468   0.920  u4/u0/_n00131 (u4/u0/N8)
     LUT2:I1->O            1   0.468   0.920  u4/u0/_n00132 (u4/u0/_n0013)
     FDE:CE                    0.687          u4/u0/sclka
    ----------------------------------------
    Total                      6.405ns (2.615ns logic, 3.790ns route)
                                       (40.8% logic, 59.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'u4/u0/sclkb:Q'
  Clock period: 8.167ns (frequency: 122.444MHz)
  Total number of paths / destination ports: 133 / 12
-------------------------------------------------------------------------
Delay:               8.167ns (Levels of Logic = 3)
  Source:            u4/u0/c1_3 (FF)
  Destination:       u4/u0/d1_0 (FF)
  Source Clock:      u4/u0/sclkb:Q rising
  Destination Clock: u4/u0/sclkb:Q rising

  Data Path: u4/u0/c1_3 to u4/u0/d1_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            4   0.992   1.520  u4/u0/c1_3 (u4/u0/c1_3)
     LUT4:I0->O            3   0.468   1.320  u4/u0/Ker71 (u4/u0/N7)
     MUXF5:S->O            7   0.725   1.950  u4/u0/_n0039 (u4/u0/_n0039)
     LUT3:I2->O            1   0.468   0.000  u4/u0/_n0021<1>1 (u4/u0/_n0021<1>)
     FDC:D                     0.724          u4/u0/d1_1
    ----------------------------------------
    Total                      8.167ns (3.377ns logic, 4.790ns route)
                                       (41.3% logic, 58.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'u4/u0/sclka:Q'
  Clock period: 6.405ns (frequency: 156.128MHz)
  Total number of paths / destination ports: 43 / 12
-------------------------------------------------------------------------
Delay:               6.405ns (Levels of Logic = 2)
  Source:            u4/u0/c0_0 (FF)
  Destination:       u4/u0/sclkb (FF)
  Source Clock:      u4/u0/sclka:Q rising
  Destination Clock: u4/u0/sclka:Q rising

  Data Path: u4/u0/c0_0 to u4/u0/sclkb
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              7   0.992   1.950  u4/u0/c0_0 (u4/u0/c0_0)
     LUT4:I1->O            1   0.468   0.920  u4/u0/_n00151 (u4/u0/N20)
     LUT2:I1->O            1   0.468   0.920  u4/u0/_n00152 (u4/u0/_n0015)
     FDE:CE                    0.687          u4/u0/sclkb
    ----------------------------------------
    Total                      6.405ns (2.615ns logic, 3.790ns route)
                                       (40.8% logic, 59.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 3354 / 65
-------------------------------------------------------------------------
Offset:              12.946ns (Levels of Logic = 6)
  Source:            button<0> (PAD)
  Destination:       u6/cnt_4 (FF)
  Destination Clock: clk rising

  Data Path: button<0> to u6/cnt_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            11   0.797   2.350  button_0_IBUF (button_0_IBUF)
     LUT4:I0->O           21   0.468   3.025  u6/div_cnt<17>1 (u6/div_cnt<17>)
     LUT2:I1->O            1   0.468   0.000  u6/XNor_stagelut15 (u6/N20)
     MUXCY:S->O            1   0.515   0.000  u6/XNor_stagecy_rn_14 (u6/XNor_stage_cyo15)
     MUXCY:CI->O           3   0.058   1.320  u6/norcy_rn_0 (u6/nor_cyo1)
     LUT3:I0->O           18   0.468   2.900  u6/_n00042 (u6/_n0004)
     FDRSE:R                   0.577          u6/cnt_0
    ----------------------------------------
    Total                     12.946ns (3.351ns logic, 9.595ns route)
                                       (25.9% logic, 74.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'reg_clk1k2:O'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              2.441ns (Levels of Logic = 1)
  Source:            din_adc (PAD)
  Destination:       u7/datain_0 (FF)
  Destination Clock: reg_clk1k2:O rising

  Data Path: din_adc to u7/datain_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.797   0.920  din_adc_IBUF (din_adc_IBUF)
     FDE:D                     0.724          u7/datain_0
    ----------------------------------------
    Total                      2.441ns (1.521ns logic, 0.920ns route)
                                       (62.3% logic, 37.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk1k:Q'
  Total number of paths / destination ports: 15 / 11
-------------------------------------------------------------------------
Offset:              11.220ns (Levels of Logic = 3)
  Source:            u3/c_2 (FF)
  Destination:       tone (PAD)
  Source Clock:      clk1k:Q rising

  Data Path: u3/c_2 to tone
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             17   0.992   2.850  u3/c_2 (u3/c_2)
     LUT4:I2->O            1   0.468   0.920  tone1 (N29)
     LUT3:I2->O            1   0.468   0.920  tone2 (tone_OBUF)
     OBUF:I->O                 4.602          tone_OBUF (tone)
    ----------------------------------------
    Total                     11.220ns (6.530ns logic, 4.690ns route)
                                       (58.2% logic, 41.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              11.939ns (Levels of Logic = 2)
  Source:            clk1k (FF)
  Destination:       lcden (PAD)
  Source Clock:      clk rising

  Data Path: clk1k to lcden
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             1   0.992   0.920  clk1k (clk1k1)
     BUFG:I->O            97   0.500   4.925  clk1k_BUFG (clk1k)
     OBUF:I->O                 4.602          lcden_OBUF (lcden)
    ----------------------------------------
    Total                     11.939ns (6.094ns logic, 5.845ns route)
                                       (51.0% logic, 49.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'reg_clk1k2:O'
  Total number of paths / destination ports: 77 / 15
-------------------------------------------------------------------------
Offset:              10.254ns (Levels of Logic = 3)
  Source:            u7/dout_2 (FF)
  Destination:       dout_led<7> (PAD)
  Source Clock:      reg_clk1k2:O rising

  Data Path: u7/dout_2 to dout_led<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q             17   0.992   2.850  u7/dout_2 (u7/dout_2)
     LUT4:I1->O            1   0.468   0.000  u7/dout_led<6>1_F (u7/N106)
     MUXF5:I0->O           1   0.422   0.920  u7/dout_led<6>1 (dout_led_6_OBUF)
     OBUF:I->O                 4.602          dout_led_6_OBUF (dout_led<6>)
    ----------------------------------------
    Total                     10.254ns (6.484ns logic, 3.770ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
CPU : 68.00 / 70.11 s | Elapsed : 68.00 / 69.00 s
 
--> 

Total memory usage is 97700 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   14 (   0 filtered)
Number of infos    :    8 (   0 filtered)