top_fpga_demo.syr

总体演示程序DEMO_FPGA.rar

 st1   | 01
 st2   | 10
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 4
# Multipliers                      : 1
 8x8-bit multiplier                : 1
# Adders/Subtractors               : 28
 10-bit adder                      : 1
 16-bit adder                      : 1
 17-bit subtractor                 : 1
 18-bit adder                      : 1
 4-bit adder                       : 16
 5-bit adder                       : 2
 5-bit subtractor                  : 1
 8-bit adder                       : 5
# Counters                         : 5
 10-bit up counter                 : 1
 16-bit up counter                 : 1
 18-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 1
# Registers                        : 76
 1-bit register                    : 43
 16-bit register                   : 2
 17-bit register                   : 1
 2-bit register                    : 1
 20-bit register                   : 1
 24-bit register                   : 1
 4-bit register                    : 17
 5-bit register                    : 3
 8-bit register                    : 7
# Latches                          : 3
 8-bit latch                       : 3
# Comparators                      : 27
 10-bit comparator less            : 2
 16-bit comparator less            : 2
 17-bit comparator greater         : 5
 18-bit comparator less            : 4
 3-bit comparator less             : 1
 4-bit comparator less             : 6
 5-bit comparator greater          : 1
 5-bit comparator less             : 1
 8-bit comparator less             : 5
# Multiplexers                     : 7
 4-bit 4-to-1 multiplexer          : 7

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Reading module "mem_infor.ngo" ( "mem_infor.ngo" unchanged since last run )...
Loading core <mem_infor> for timing and area information for instance <U0>.
Register <reg_dout_15> equivalent to <dout_lcd_19> has been removed
Register <current_state_0> equivalent to <clk_tlc549> has been removed
Register <reg_dout_0> equivalent to <dout_lcd_4> has been removed
Register <reg_dout_1> equivalent to <dout_lcd_5> has been removed
Register <reg_dout_2> equivalent to <dout_lcd_6> has been removed
Register <reg_dout_3> equivalent to <dout_lcd_7> has been removed
Register <reg_dout_4> equivalent to <dout_lcd_8> has been removed
Register <reg_dout_5> equivalent to <dout_lcd_9> has been removed
Register <reg_dout_6> equivalent to <dout_lcd_10> has been removed
Register <reg_dout_7> equivalent to <dout_lcd_11> has been removed
Register <reg_dout_8> equivalent to <dout_lcd_12> has been removed
Register <reg_dout_9> equivalent to <dout_lcd_13> has been removed
Register <reg_dout_10> equivalent to <dout_lcd_14> has been removed
Register <reg_dout_11> equivalent to <dout_lcd_15> has been removed
Register <reg_dout_12> equivalent to <dout_lcd_16> has been removed
Register <reg_dout_13> equivalent to <dout_lcd_17> has been removed
Register <reg_dout_14> equivalent to <dout_lcd_18> has been removed
WARNING:Xst:1989 - Unit <electronic_organ>: instances <Mcompar__n0010>, <Mcompar__n0017> of unit <LPM_COMPARE_11> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <electronic_organ>: instances <Mcompar__n0019>, <Mcompar__n0016> of unit <LPM_COMPARE_11> are equivalent, second instance is removed

Optimizing unit <top_fpga_demo> ...

Optimizing unit <button1> ...

Optimizing unit <page3> ...

Optimizing unit <page1> ...

Optimizing unit <page4> ...

Optimizing unit <digital_voltmeter> ...

Optimizing unit <mode_cymometer> ...

Optimizing unit <digital_clk> ...
WARNING:Xst:1710 - FF/Latch  <d_3> (without init value) has a constant value of 0 in block <digital_clk>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <d0_3> (without init value) has a constant value of 0 in block <digital_clk>.

Optimizing unit <lcd> ...

Optimizing unit <page_step> ...

Optimizing unit <electronic_organ> ...
Loading device for application Rf_Device from file '2s100e.nph' in environment E:/Program/EDA/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_fpga_demo, actual ratio is 41.
FlipFlop u3/c_1 has been replicated 2 time(s)
FlipFlop clk1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u7/clk_tlc549 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top_fpga_demo.ngr
Top Level Output File Name         : top_fpga_demo
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 41

Macro Statistics :
# Registers                        : 60
#      1-bit register              : 24
#      16-bit register             : 2
#      17-bit register             : 1
#      2-bit register              : 1
#      20-bit register             : 1
#      24-bit register             : 1
#      3-bit register              : 3
#      4-bit register              : 17
#      5-bit register              : 3
#      8-bit register              : 7
# Counters                         : 2
#      18-bit up counter           : 1
#      4-bit up counter            : 1
# Multiplexers                     : 7
#      4-bit 4-to-1 multiplexer    : 7
# Adders/Subtractors               : 28
#      10-bit adder                : 1
#      16-bit adder                : 1
#      17-bit subtractor           : 1
#      18-bit adder                : 1
#      4-bit adder                 : 16
#      5-bit adder                 : 2
#      5-bit subtractor            : 1
#      8-bit adder                 : 5
# Multipliers                      : 1
#      8x8-bit multiplier          : 1
# Comparators                      : 27
#      10-bit comparator less      : 2
#      16-bit comparator less      : 2
#      17-bit comparator greater   : 5
#      18-bit comparator less      : 4
#      3-bit comparator less       : 1
#      4-bit comparator less       : 6
#      5-bit comparator greater    : 1
#      5-bit comparator less       : 1
#      8-bit comparator less       : 5

Cell Usage :
# BELS                             : 1271
#      GND                         : 2
#      INV                         : 46
#      LUT1                        : 137
#      LUT2                        : 141
#      LUT2_L                      : 1
#      LUT3                        : 135
#      LUT4                        : 313
#      LUT4_D                      : 1
#      LUT4_L                      : 23
#      MUXCY                       : 263
#      MUXF5                       : 24
#      VCC                         : 2
#      XORCY                       : 183
# FlipFlops/Latches                : 338
#      FD                          : 25
#      FDC                         : 63
#      FDC_1                       : 12
#      FDCE                        : 6
#      FDCPE                       : 4
#      FDE                         : 104
#      FDE_1                       : 14
#      FDP_1                       : 1
#      FDR                         : 30
#      FDRE                        : 7
#      FDRSE                       : 18
#      FDS                         : 29
#      FDSE                        : 1
#      LD                          : 24
# RAMS                             : 2
#      RAMB4_S8                    : 2
# Clock Buffers                    : 3
#      BUFG                        : 2
#      BUFGP                       : 1
# IO Buffers                       : 40
#      IBUF                        : 11
#      OBUF                        : 29
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100epq208-6 

 Number of Slices:                     460  out of   1200    38%  
 Number of Slice Flip Flops:           338  out of   2400    14%  
 Number of 4 input LUTs:               751  out of   2400    31%  
 Number of bonded IOBs:                 41  out of    146    28%  
 Number of BRAMs:                        2  out of     10    20%  
 Number of GCLKs:                        3  out of      4    75%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 86    |
clk1k:Q                            | BUFG                   | 93    |
u4/u1/_n0001(u4/u1/_n00012:O)      | NONE(*)(u4/u1/dout_6)  | 8     |
u8/_n0001(u8/_n00012:O)            | NONE(*)(u8/dout_4)     | 8     |
u5/u0/_n0001(u5/u0/_n00012:O)      | NONE(*)(u5/u0/dout_3)  | 8     |
reg_clk1k1(reg_clk1k2:O)           | BUFG(*)(u7/dout_lcd_15)| 112   |
clk1:Q                             | NONE                   | 9     |
u4/u0/sclkb:Q                      | NONE                   | 8     |
u4/u0/sclka:Q                      | NONE                   | 8     |
-----------------------------------+------------------------+-------+
(*) These 4 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 22.306ns (Maximum Frequency: 44.831MHz)
   Minimum input arrival time before clock: 12.946ns
   Maximum output required time after clock: 11.939ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 14.156ns (frequency: 70.641MHz)
  Total number of paths / destination ports: 18521 / 171
-------------------------------------------------------------------------
Delay:               14.156ns (Levels of Logic = 5)
  Source:            clk1k (FF)