top_fpga_demo.syr

总体演示程序DEMO_FPGA.rar

Unit <digital_clk> synthesized.


Synthesizing Unit <button1>.
    Related source file is "E:/DEMO_FPGA/button1.vhd".
    Found 8-bit adder for signal <$n0002> created at line 44.
    Found 8-bit comparator less for signal <$n0003> created at line 44.
    Found 8-bit register for signal <delay>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <button1> synthesized.


Synthesizing Unit <page3>.
    Related source file is "E:/DEMO_FPGA/page3.vhd".
WARNING:Xst:737 - Found 8-bit latch for signal <dout>.
Unit <page3> synthesized.


Synthesizing Unit <digital_voltmeter>.
    Related source file is "E:/DEMO_FPGA/DEMO_ADC.vhd".
    Found finite state machine <FSM_0> for signal <current_state1>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 8                                              |
    | Inputs             | 5                                              |
    | Outputs            | 3                                              |
    | Clock              | clk1k (rising_edge)                            |
    | Power Up State     | st0                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <current_state2>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 5                                              |
    | Inputs             | 0                                              |
    | Outputs            | 5                                              |
    | Clock              | clk1k (rising_edge)                            |
    | Power Up State     | st0                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit register for signal <shift>.
    Found 2-bit register for signal <cs_led>.
    Found 20-bit register for signal <dout_lcd>.
    Found 1-bit register for signal <clk_tlc549>.
    Found 17-bit comparator greater for signal <$n0006> created at line 96.
    Found 17-bit comparator greater for signal <$n0007> created at line 96.
    Found 17-bit comparator greater for signal <$n0008> created at line 97.
    Found 17-bit comparator greater for signal <$n0009> created at line 98.
    Found 17-bit comparator greater for signal <$n0010> created at line 99.
    Found 8x8-bit multiplier for signal <$n0030> created at line 74.
    Found 17-bit subtractor for signal <$n0031> created at line 96.
    Found 4-bit adder for signal <$n0033> created at line 96.
    Found 4-bit adder for signal <$n0034> created at line 97.
    Found 4-bit adder for signal <$n0035> created at line 98.
    Found 4-bit adder for signal <$n0036> created at line 99.
    Found 4-bit adder for signal <$n0037> created at line 100.
    Found 3-bit comparator less for signal <$n0048> created at line 72.
    Found 3-bit up counter for signal <cnt>.
    Found 1-bit register for signal <current_state<0>>.
    Found 4-bit register for signal <d1>.
    Found 4-bit register for signal <d2>.
    Found 4-bit register for signal <d3>.
    Found 4-bit register for signal <d4>.
    Found 4-bit register for signal <d5>.
    Found 8-bit register for signal <datain>.
    Found 5-bit register for signal <dout>.
    Found 17-bit register for signal <reg>.
    Found 8-bit register for signal <reg_datain>.
    Found 16-bit register for signal <reg_din>.
    Found 16-bit register for signal <reg_dout>.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred 118 D-type flip-flop(s).
	inferred   6 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
	inferred   6 Comparator(s).
Unit <digital_voltmeter> synthesized.


Synthesizing Unit <electronic_organ>.
    Related source file is "E:/DEMO_FPGA/electronic_organ.vhd".
    Found 1-bit register for signal <tone>.
    Found 18-bit adder for signal <$n0009> created at line 51.
    Found 18-bit comparator less for signal <$n0010> created at line 52.
    Found 18-bit comparator less for signal <$n0016> created at line 53.
    Found 18-bit comparator less for signal <$n0017> created at line 52.
    Found 18-bit comparator less for signal <$n0019> created at line 53.
    Found 18-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   4 Comparator(s).
Unit <electronic_organ> synthesized.


Synthesizing Unit <top_mode_cymometer>.
    Related source file is "E:/DEMO_FPGA/top_mode_cymometer.vhd".
Unit <top_mode_cymometer> synthesized.


Synthesizing Unit <mode_clk>.
    Related source file is "E:/DEMO_FPGA/mode_clk.vhd".
Unit <mode_clk> synthesized.


Synthesizing Unit <page_step>.
    Related source file is "E:/DEMO_FPGA/page_step.vhd".
    Found finite state machine <FSM_2> for signal <current_state>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 19                                             |
    | Inputs             | 4                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | ireset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | st0                                            |
    | Power Up State     | st0                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 5-bit adder for signal <$n0000> created at line 67.
    Found 5-bit subtractor for signal <$n0001> created at line 77.
    Found 5-bit comparator less for signal <$n0012> created at line 67.
    Found 5-bit comparator greater for signal <$n0013> created at line 77.
    Found 5-bit register for signal <c>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   5 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   2 Comparator(s).
Unit <page_step> synthesized.


Synthesizing Unit <keyboards>.
    Related source file is "E:/DEMO_FPGA/keyboards.vhd".
Unit <keyboards> synthesized.


Synthesizing Unit <lcd>.
    Related source file is "E:/DEMO_FPGA/lcd_driver.vhd".
INFO:Xst:1799 - State write_data3 is never reached in FSM <current_state>.
INFO:Xst:1799 - State set_location2 is never reached in FSM <current_state>.
INFO:Xst:1799 - State set_cgram_location is never reached in FSM <current_state>.
INFO:Xst:1799 - State write_cgram is never reached in FSM <current_state>.
    Found finite state machine <FSM_3> for signal <current_state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 10                                             |
    | Inputs             | 2                                              |
    | Outputs            | 8                                              |
    | Clock              | clk (falling_edge)                             |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | set_dlnf                                       |
    | Power Up State     | set_dlnf                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <lcdda>.
    Found 5-bit register for signal <lcd_address>.
    Found 8-bit register for signal <data>.
    Found 5-bit adder for signal <$n0013> created at line 63.
    Found 5-bit register for signal <cnt2>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  19 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <lcd> synthesized.


Synthesizing Unit <page_information>.
    Related source file is "E:/DEMO_FPGA/mem_inform.vhd".
Unit <page_information> synthesized.


Synthesizing Unit <top_fpga_demo>.
    Related source file is "E:/DEMO_FPGA/Top_FPGA_demo.vhd".
    Found 10-bit comparator less for signal <$n0004> created at line 181.
    Found 10-bit comparator less for signal <$n0005> created at line 181.
    Found 16-bit comparator less for signal <$n0006> created at line 170.
    Found 16-bit comparator less for signal <$n0007> created at line 170.
    Found 10-bit adder for signal <$n0010> created at line 180.
    Found 16-bit adder for signal <$n0011> created at line 169.
    Found 1-bit register for signal <clk1>.
    Found 1-bit register for signal <clk1k>.
    Found 16-bit up counter for signal <cnt>.
    Found 10-bit up counter for signal <cnt0>.
    Summary:
	inferred   2 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   4 Comparator(s).
Unit <top_fpga_demo> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
INFO:Xst:1784 - HDL ADVISOR - Multiplier(s) is(are) identified in your design. You can improve the performance of your multiplier by using the pipeline feature available with mult_style attribute.
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <FSM_3> on signal <current_state[1:8]> with speed1 encoding.
--------------------------------
 State              | Encoding
--------------------------------
 set_dlnf           | 10000000
 clear_lcd          | 01000000
 set_cursor         | 00100000
 set_location3      | 00000001
 write_data2        | 00010000
 set_dcb            | 00001000
 set_location       | 00000100
 write_data         | 00000010
 write_data3        | unreached
 set_location2      | unreached
 set_cgram_location | unreached
 write_cgram        | unreached
--------------------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <FSM_2> on signal <current_state[1:4]> with gray encoding.
-------------------
 State | Encoding
-------------------
 st0   | 0000
 st1   | 0010
 st2   | 0110
 st3   | 0011
 st4   | 0111
 st5   | 0001
 st6   | 0101
 st7   | 0100
 st8   | 1100
 st9   | 1101
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <FSM_1> on signal <current_state2[1:5]> with speed1 encoding.
-------------------
 State | Encoding
-------------------
 st0   | 10000
 st1   | 01000
 st2   | 00100
 st3   | 00010
 st4   | 00001
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <current_state1[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 st0   | 00