top_fpga_demo.syr

总体演示程序DEMO_FPGA.rar

Release 7.1.01i - xst H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: top_fpga_demo.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "top_fpga_demo.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "top_fpga_demo"
Output Format                      : NGC
Target Device                      : xc2s100e-6-pq208

---- Source Options
Top Module Name                    : top_fpga_demo
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : top_fpga_demo.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3498 - No primary, secondary unit in the file "E:/DEMO_FPGA/mem_infor.vhd. Ignore this file from project file "top_fpga_demo_vhdl.prj".
Compiling vhdl file "E:/DEMO_FPGA/page4.vhd" in Library work.
Architecture behavioral of Entity page4 is up to date.
Compiling vhdl file "E:/DEMO_FPGA/mode_cymometer.vhd" in Library work.
Architecture behavioral of Entity mode_cymometer is up to date.
Compiling vhdl file "E:/DEMO_FPGA/digital_clk.vhd" in Library work.
Architecture behavioral of Entity digital_clk is up to date.
Compiling vhdl file "E:/DEMO_FPGA/page_dclk.vhd" in Library work.
Architecture digital_clock of Entity page1 is up to date.
Compiling vhdl file "E:/DEMO_FPGA/button1.vhd" in Library work.
Architecture keyboards of Entity button1 is up to date.
Compiling vhdl file "E:/DEMO_FPGA/mem_inform.vhd" in Library work.
Architecture data of Entity page_information is up to date.
Compiling vhdl file "E:/DEMO_FPGA/lcd_driver.vhd" in Library work.
Architecture driver of Entity lcd is up to date.
Compiling vhdl file "E:/DEMO_FPGA/keyboards.vhd" in Library work.
Architecture behavioral of Entity keyboards is up to date.
Compiling vhdl file "E:/DEMO_FPGA/page_step.vhd" in Library work.
Architecture behavioral of Entity page_step is up to date.
Compiling vhdl file "E:/DEMO_FPGA/mode_clk.vhd" in Library work.
Architecture behavioral of Entity mode_clk is up to date.
Compiling vhdl file "E:/DEMO_FPGA/top_mode_cymometer.vhd" in Library work.
Architecture behavioral of Entity top_mode_cymometer is up to date.
Compiling vhdl file "E:/DEMO_FPGA/electronic_organ.vhd" in Library work.
Architecture behavioral of Entity electronic_organ is up to date.
Compiling vhdl file "E:/DEMO_FPGA/DEMO_ADC.vhd" in Library work.
Architecture adc of Entity digital_voltmeter is up to date.
Compiling vhdl file "E:/DEMO_FPGA/page3.vhd" in Library work.
Architecture behavioral of Entity page3 is up to date.
Compiling vhdl file "E:/DEMO_FPGA/Top_FPGA_demo.vhd" in Library work.
Architecture behavioral of Entity top_fpga_demo is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_fpga_demo> (Architecture <behavioral>).
Entity <top_fpga_demo> analyzed. Unit <top_fpga_demo> generated.

Analyzing Entity <page_information> (Architecture <data>).
WARNING:Xst:766 - "E:/DEMO_FPGA/mem_inform.vhd" line 41: Generating a Black Box for component <mem_infor>.
Entity <page_information> analyzed. Unit <page_information> generated.

Analyzing Entity <lcd> (Architecture <driver>).
Entity <lcd> analyzed. Unit <lcd> generated.

Analyzing Entity <keyboards> (Architecture <behavioral>).
Entity <keyboards> analyzed. Unit <keyboards> generated.

Analyzing Entity <button1> (Architecture <keyboards>).
Entity <button1> analyzed. Unit <button1> generated.

Analyzing Entity <page_step> (Architecture <behavioral>).
Entity <page_step> analyzed. Unit <page_step> generated.

Analyzing Entity <mode_clk> (Architecture <behavioral>).
Entity <mode_clk> analyzed. Unit <mode_clk> generated.

Analyzing Entity <digital_clk> (Architecture <behavioral>).
Entity <digital_clk> analyzed. Unit <digital_clk> generated.

Analyzing Entity <page1> (Architecture <digital_clock>).
Entity <page1> analyzed. Unit <page1> generated.

Analyzing Entity <top_mode_cymometer> (Architecture <behavioral>).
WARNING:Xst:752 - "E:/DEMO_FPGA/top_mode_cymometer.vhd" line 66: Unconnected input port 'ireset' of component 'mode_cymometer' is tied to default value.
Entity <top_mode_cymometer> analyzed. Unit <top_mode_cymometer> generated.

Analyzing Entity <page4> (Architecture <behavioral>).
WARNING:Xst:819 - "E:/DEMO_FPGA/page4.vhd" line 42: The following signals are missing in the process sensitivity list:
   dint<23>, dint<22>, dint<21>, dint<20>, dint<19>, dint<18>, dint<17>, dint<16>, dint<15>, dint<14>, dint<13>, dint<12>, dint<11>, dint<10>, dint<9>, dint<8>, dint<7>, dint<6>, dint<5>, dint<4>, dint<3>, dint<2>, dint<1>, dint<0>.
Entity <page4> analyzed. Unit <page4> generated.

Analyzing Entity <mode_cymometer> (Architecture <behavioral>).
Entity <mode_cymometer> analyzed. Unit <mode_cymometer> generated.

Analyzing Entity <electronic_organ> (Architecture <behavioral>).
Entity <electronic_organ> analyzed. Unit <electronic_organ> generated.

Analyzing Entity <digital_voltmeter> (Architecture <adc>).
WARNING:Xst:819 - "E:/DEMO_FPGA/DEMO_ADC.vhd" line 150: The following signals are missing in the process sensitivity list:
   reg_datain.
INFO:Xst:1304 - Contents of register <cs_tlc549> in unit <digital_voltmeter> never changes during circuit operation. The register is replaced by logic.
Entity <digital_voltmeter> analyzed. Unit <digital_voltmeter> generated.

Analyzing Entity <page3> (Architecture <behavioral>).
WARNING:Xst:819 - "E:/DEMO_FPGA/page3.vhd" line 41: The following signals are missing in the process sensitivity list:
   dint<19>, dint<18>, dint<17>, dint<16>, dint<15>, dint<14>, dint<13>, dint<12>, dint<11>, dint<10>, dint<9>, dint<8>, dint<7>, dint<6>, dint<5>, dint<4>, dint<3>, dint<2>, dint<1>, dint<0>.
Entity <page3> analyzed. Unit <page3> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <mode_cymometer>.
    Related source file is "E:/DEMO_FPGA/mode_cymometer.vhd".
WARNING:Xst:1780 - Signal <current_state> is never used or assigned.
    Found 24-bit register for signal <dout>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0015>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0016>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0017>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0018>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0019>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0020>.
    Found 4-bit adder for signal <$n0022> created at line 79.
    Found 4-bit adder for signal <$n0023> created at line 78.
    Found 4-bit adder for signal <$n0024> created at line 77.
    Found 4-bit adder for signal <$n0025> created at line 76.
    Found 4-bit adder for signal <$n0026> created at line 75.
    Found 4-bit adder for signal <$n0027> created at line 74.
    Found 4-bit register for signal <cnt1>.
    Found 4-bit register for signal <cnt2>.
    Found 4-bit register for signal <cnt3>.
    Found 4-bit register for signal <cnt4>.
    Found 4-bit register for signal <cnt5>.
    Found 4-bit register for signal <cnt6>.
    Found 1-bit register for signal <kd>.
    Found 1-bit register for signal <ris_a>.
    Found 1-bit register for signal <ris_b>.
    Summary:
	inferred  51 D-type flip-flop(s).
	inferred   6 Adder/Subtractor(s).
	inferred  24 Multiplexer(s).
Unit <mode_cymometer> synthesized.


Synthesizing Unit <page4>.
    Related source file is "E:/DEMO_FPGA/page4.vhd".
WARNING:Xst:737 - Found 8-bit latch for signal <dout>.
Unit <page4> synthesized.


Synthesizing Unit <page1>.
    Related source file is "E:/DEMO_FPGA/page_dclk.vhd".
WARNING:Xst:737 - Found 8-bit latch for signal <dout>.
Unit <page1> synthesized.


Synthesizing Unit <digital_clk>.
    Related source file is "E:/DEMO_FPGA/digital_clk.vhd".
    Found 4-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit adder for signal <$n0022>.
    Found 4-bit adder for signal <$n0023> created at line 48.
    Found 4-bit adder for signal <$n0024> created at line 50.
    Found 4-bit adder for signal <$n0025> created at line 64.
    Found 4-bit adder for signal <$n0026> created at line 66.
    Found 4-bit comparator less for signal <$n0027> created at line 48.
    Found 4-bit comparator less for signal <$n0028> created at line 50.
    Found 4-bit comparator less for signal <$n0029> created at line 66.
    Found 4-bit comparator less for signal <$n0030> created at line 64.
    Found 4-bit comparator less for signal <$n0032> created at line 81.
    Found 4-bit comparator less for signal <$n0033> created at line 82.
    Found 4-bit register for signal <c>.
    Found 4-bit register for signal <c0>.
    Found 4-bit up counter for signal <c1>.
    Found 4-bit register for signal <d>.
    Found 4-bit register for signal <d0>.
    Found 4-bit register for signal <d1>.
    Found 1-bit register for signal <sclka>.
    Found 1-bit register for signal <sclkb>.
    Summary:
	inferred   1 Counter(s).
	inferred  22 D-type flip-flop(s).
	inferred   5 Adder/Subtractor(s).
	inferred   6 Comparator(s).
	inferred   4 Multiplexer(s).