digital_clk.twr

总体演示程序DEMO_FPGA.rar

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Release 7.1.01i Trace H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

E:/Program/EDA/Xilinx/bin/nt/trce.exe -ise e:\demo_fpga\DEMO_FPGA.ise -intstyle
ise -e 3 -l 3 -s 6 -xml digital_clk digital_clk.ncd -o digital_clk.twr
digital_clk.pcf


Design file:              digital_clk.ncd
Physical constraint file: digital_clk.pcf
Device,speed:             xc2s100e,-6 (PRODUCTION 1.18 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
oh<0>       |    8.693(R)|clk_BUFGP         |   0.000|
oh<1>       |    9.887(R)|clk_BUFGP         |   0.000|
oh<2>       |    9.289(R)|clk_BUFGP         |   0.000|
oh<3>       |    9.488(R)|clk_BUFGP         |   0.000|
oh<4>       |    9.978(R)|clk_BUFGP         |   0.000|
oh<5>       |    9.494(R)|clk_BUFGP         |   0.000|
oh<6>       |    9.466(R)|clk_BUFGP         |   0.000|
oh<7>       |    9.557(R)|clk_BUFGP         |   0.000|
om<0>       |    9.423(R)|clk_BUFGP         |   0.000|
om<1>       |    8.910(R)|clk_BUFGP         |   0.000|
om<2>       |    9.057(R)|clk_BUFGP         |   0.000|
om<3>       |    9.392(R)|clk_BUFGP         |   0.000|
om<4>       |    9.562(R)|clk_BUFGP         |   0.000|
om<5>       |    9.160(R)|clk_BUFGP         |   0.000|
om<6>       |    9.461(R)|clk_BUFGP         |   0.000|
om<7>       |    8.932(R)|clk_BUFGP         |   0.000|
os<0>       |    9.037(R)|clk_BUFGP         |   0.000|
os<1>       |    9.281(R)|clk_BUFGP         |   0.000|
os<2>       |    9.384(R)|clk_BUFGP         |   0.000|
os<3>       |    8.859(R)|clk_BUFGP         |   0.000|
os<4>       |    8.561(R)|clk_BUFGP         |   0.000|
os<5>       |    8.857(R)|clk_BUFGP         |   0.000|
os<6>       |    8.972(R)|clk_BUFGP         |   0.000|
os<7>       |    9.183(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    9.132|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Fri Mar 25 03:08:04 2005
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Peak Memory Usage: 69 MB