📄 demo_all.twr
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Release 7.1.01i Trace H.39
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
E:/Program/EDA/Xilinx/bin/nt/trce.exe -ise e:\demo_fpga\DEMO_FPGA.ise -intstyle
ise -e 3 -l 3 -s 6 -xml demo_all demo_all.ncd -o demo_all.twr demo_all.pcf
Design file: demo_all.ncd
Physical constraint file: demo_all.pcf
Device,speed: xc2s100e,-6 (PRODUCTION 1.18 2005-01-22)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
itclk | 9.936(R)| -3.288(R)|clk_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock mode<0>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
button<0> | -6.295(F)| 7.387(F)|_n0002 | 0.000|
| -7.341(F)| 7.818(F)|_n0003 | 0.000|
button<1> | -6.188(F)| 7.280(F)|_n0002 | 0.000|
| -7.084(F)| 7.540(F)|_n0003 | 0.000|
| -2.628(F)| 3.180(F)|_n0124 | 0.000|
button<2> | -5.825(F)| 6.917(F)|_n0002 | 0.000|
| -7.827(F)| 8.304(F)|_n0003 | 0.000|
button<3> | -5.825(F)| 6.917(F)|_n0002 | 0.000|
| -7.503(F)| 7.959(F)|_n0003 | 0.000|
button<4> | -5.811(F)| 6.288(F)|_n0002 | 0.000|
| -7.317(F)| 8.409(F)|_n0003 | 0.000|
button<5> | -5.018(F)| 6.110(F)|_n0002 | 0.000|
| -7.696(F)| 8.173(F)|_n0003 | 0.000|
button<6> | -5.018(F)| 6.110(F)|_n0002 | 0.000|
| -7.435(F)| 7.891(F)|_n0003 | 0.000|
button<7> | -5.018(F)| 6.110(F)|_n0002 | 0.000|
| -6.827(F)| 7.304(F)|_n0003 | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock mode<1>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
button<0> | -6.628(F)| 7.720(F)|_n0002 | 0.000|
| -3.626(F)| 4.103(F)|_n0003 | 0.000|
| -6.759(F)| 7.311(F)|_n0123 | 0.000|
button<1> | -6.521(F)| 7.613(F)|_n0002 | 0.000|
| -3.369(F)| 3.825(F)|_n0003 | 0.000|
| -2.804(F)| 3.356(F)|_n0124 | 0.000|
button<2> | -6.158(F)| 7.250(F)|_n0002 | 0.000|
| -4.112(F)| 4.589(F)|_n0003 | 0.000|
| -7.031(F)| 7.583(F)|_n0123 | 0.000|
button<3> | -6.158(F)| 7.250(F)|_n0002 | 0.000|
| -3.788(F)| 4.244(F)|_n0003 | 0.000|
| -7.037(F)| 7.599(F)|_n0123 | 0.000|
button<4> | -6.144(F)| 6.621(F)|_n0002 | 0.000|
| -3.602(F)| 4.694(F)|_n0003 | 0.000|
button<5> | -5.351(F)| 6.443(F)|_n0002 | 0.000|
| -3.981(F)| 4.458(F)|_n0003 | 0.000|
button<6> | -5.351(F)| 6.443(F)|_n0002 | 0.000|
| -3.720(F)| 4.176(F)|_n0003 | 0.000|
button<7> | -5.351(F)| 6.443(F)|_n0002 | 0.000|
| -3.112(F)| 3.589(F)|_n0003 | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock mode<2>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
button<0> | -5.041(F)| 6.133(F)|_n0002 | 0.000|
| -3.762(F)| 4.239(F)|_n0003 | 0.000|
| -5.952(F)| 6.504(F)|_n0123 | 0.000|
button<1> | -4.934(F)| 6.026(F)|_n0002 | 0.000|
| -3.505(F)| 3.961(F)|_n0003 | 0.000|
| -3.247(F)| 3.799(F)|_n0124 | 0.000|
button<2> | -4.571(F)| 5.663(F)|_n0002 | 0.000|
| -4.248(F)| 4.725(F)|_n0003 | 0.000|
| -6.224(F)| 6.776(F)|_n0123 | 0.000|
button<3> | -4.571(F)| 5.663(F)|_n0002 | 0.000|
| -3.924(F)| 4.380(F)|_n0003 | 0.000|
| -6.230(F)| 6.792(F)|_n0123 | 0.000|
button<4> | -4.557(F)| 5.034(F)|_n0002 | 0.000|
| -3.738(F)| 4.830(F)|_n0003 | 0.000|
button<5> | -3.764(F)| 4.856(F)|_n0002 | 0.000|
| -4.117(F)| 4.594(F)|_n0003 | 0.000|
button<6> | -3.764(F)| 4.856(F)|_n0002 | 0.000|
| -3.856(F)| 4.312(F)|_n0003 | 0.000|
button<7> | -3.764(F)| 4.856(F)|_n0002 | 0.000|
| -3.248(F)| 3.725(F)|_n0003 | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock mode<3>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
button<0> | -6.648(F)| 7.740(F)|_n0002 | 0.000|
| -7.694(F)| 8.171(F)|_n0003 | 0.000|
| -4.949(F)| 5.501(F)|_n0123 | 0.000|
button<1> | -6.541(F)| 7.633(F)|_n0002 | 0.000|
| -7.437(F)| 7.893(F)|_n0003 | 0.000|
| -3.217(F)| 3.769(F)|_n0124 | 0.000|
button<2> | -6.178(F)| 7.270(F)|_n0002 | 0.000|
| -8.180(F)| 8.657(F)|_n0003 | 0.000|
| -5.221(F)| 5.773(F)|_n0123 | 0.000|
button<3> | -6.178(F)| 7.270(F)|_n0002 | 0.000|
| -7.856(F)| 8.312(F)|_n0003 | 0.000|
| -5.227(F)| 5.789(F)|_n0123 | 0.000|
button<4> | -6.164(F)| 6.641(F)|_n0002 | 0.000|
| -7.670(F)| 8.762(F)|_n0003 | 0.000|
button<5> | -5.371(F)| 6.463(F)|_n0002 | 0.000|
| -8.049(F)| 8.526(F)|_n0003 | 0.000|
button<6> | -5.371(F)| 6.463(F)|_n0002 | 0.000|
| -7.788(F)| 8.244(F)|_n0003 | 0.000|
button<7> | -5.371(F)| 6.463(F)|_n0002 | 0.000|
| -7.180(F)| 7.657(F)|_n0003 | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock mode<4>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
button<0> | -6.922(F)| 8.014(F)|_n0002 | 0.000|
| -7.968(F)| 8.445(F)|_n0003 | 0.000|
| -5.309(F)| 5.861(F)|_n0123 | 0.000|
button<1> | -6.815(F)| 7.907(F)|_n0002 | 0.000|
| -7.711(F)| 8.167(F)|_n0003 | 0.000|
| -2.876(F)| 3.428(F)|_n0124 | 0.000|
button<2> | -6.452(F)| 7.544(F)|_n0002 | 0.000|
| -8.454(F)| 8.931(F)|_n0003 | 0.000|
| -5.581(F)| 6.133(F)|_n0123 | 0.000|
button<3> | -6.452(F)| 7.544(F)|_n0002 | 0.000|
| -8.130(F)| 8.586(F)|_n0003 | 0.000|
| -5.587(F)| 6.149(F)|_n0123 | 0.000|
button<4> | -6.438(F)| 6.915(F)|_n0002 | 0.000|
| -7.944(F)| 9.036(F)|_n0003 | 0.000|
button<5> | -5.645(F)| 6.737(F)|_n0002 | 0.000|
| -8.323(F)| 8.800(F)|_n0003 | 0.000|
button<6> | -5.645(F)| 6.737(F)|_n0002 | 0.000|
| -8.062(F)| 8.518(F)|_n0003 | 0.000|
button<7> | -5.645(F)| 6.737(F)|_n0002 | 0.000|
| -7.454(F)| 7.931(F)|_n0003 | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock mode<5>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
button<0> | -7.672(F)| 8.764(F)|_n0002 | 0.000|
| -8.718(F)| 9.195(F)|_n0003 | 0.000|
| -4.686(F)| 5.238(F)|_n0123 | 0.000|
button<1> | -7.565(F)| 8.657(F)|_n0002 | 0.000|
| -8.461(F)| 8.917(F)|_n0003 | 0.000|
| -2.762(F)| 3.314(F)|_n0124 | 0.000|
button<2> | -7.202(F)| 8.294(F)|_n0002 | 0.000|
| -9.204(F)| 9.681(F)|_n0003 | 0.000|
| -4.958(F)| 5.510(F)|_n0123 | 0.000|
button<3> | -7.202(F)| 8.294(F)|_n0002 | 0.000|
| -8.880(F)| 9.336(F)|_n0003 | 0.000|
| -4.964(F)| 5.526(F)|_n0123 | 0.000|
button<4> | -7.188(F)| 7.665(F)|_n0002 | 0.000|
| -8.694(F)| 9.786(F)|_n0003 | 0.000|
button<5> | -6.395(F)| 7.487(F)|_n0002 | 0.000|
| -9.073(F)| 9.550(F)|_n0003 | 0.000|
button<6> | -6.395(F)| 7.487(F)|_n0002 | 0.000|
| -8.812(F)| 9.268(F)|_n0003 | 0.000|
button<7> | -6.395(F)| 7.487(F)|_n0002 | 0.000|
| -8.204(F)| 8.681(F)|_n0003 | 0.000|
------------+------------+------------+------------------+--------+
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
lcden | 12.930(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock mode<0> to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
cs<0> | 12.754(F)|_n0122 | 0.000|
cs<1> | 14.873(F)|_n0122 | 0.000|
led<0> | 14.873(F)|_n0122 | 0.000|
led<1> | 14.539(F)|_n0122 | 0.000|
led<2> | 14.289(F)|_n0122 | 0.000|
led<3> | 13.101(F)|_n0122 | 0.000|
led<4> | 14.530(F)|_n0122 | 0.000|
led<5> | 14.501(F)|_n0122 | 0.000|
led<6> | 14.678(F)|_n0122 | 0.000|
led<7> | 14.678(F)|_n0122 | 0.000|
led_shift<0>| 13.332(F)|_n0124 | 0.000|
led_shift<1>| 14.210(F)|_n0124 | 0.000|
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