uart.syr

总体演示程序DEMO_FPGA.rar

Design Statistics
# IOs                              : 17

Macro Statistics :
# Registers                        : 16
#      1-bit register              : 12
#      13-bit register             : 2
#      3-bit register              : 2
# Adders/Subtractors               : 4
#      11-bit adder                : 1
#      13-bit adder                : 3
# Comparators                      : 6
#      11-bit comparator less      : 2
#      13-bit comparator less      : 2
#      3-bit comparator less       : 2

Cell Usage :
# BELS                             : 199
#      GND                         : 1
#      INV                         : 8
#      LUT1                        : 22
#      LUT1_L                      : 25
#      LUT2                        : 16
#      LUT2_L                      : 1
#      LUT3                        : 8
#      LUT3_L                      : 2
#      LUT4                        : 19
#      LUT4_D                      : 1
#      LUT4_L                      : 2
#      MUXCY                       : 52
#      VCC                         : 1
#      XORCY                       : 41
# FlipFlops/Latches                : 46
#      FD                          : 1
#      FD_1                        : 5
#      FDE                         : 6
#      FDE_1                       : 8
#      FDR                         : 24
#      FDRE                        : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 16
#      IBUF                        : 7
#      OBUF                        : 9
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100epq208-6 

 Number of Slices:                      65  out of   1200     5%  
 Number of Slice Flip Flops:            46  out of   2400     1%  
 Number of 4 input LUTs:                96  out of   2400     4%  
 Number of bonded IOBs:                 17  out of    146    11%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 39    |
bclk:Q                             | NONE                   | 6     |
tclk:Q                             | NONE                   | 1     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 11.659ns (Maximum Frequency: 85.771MHz)
   Minimum input arrival time before clock: 6.110ns
   Maximum output required time after clock: 6.514ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 11.659ns (frequency: 85.771MHz)
  Total number of paths / destination ports: 3399 / 65
-------------------------------------------------------------------------
Delay:               11.659ns (Levels of Logic = 17)
  Source:            c_0 (FF)
  Destination:       c_11 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: c_0 to c_11
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.992   1.150  c_0 (c_0)
     INV:I->O              1   0.468   0.000  uart__n0032<0>lut_INV_0 (N7)
     MUXCY:S->O            1   0.515   0.000  uart__n0032<0>cy (uart__n0032<0>_cyo)
     MUXCY:CI->O           1   0.058   0.000  uart__n0032<1>cy (uart__n0032<1>_cyo)
     MUXCY:CI->O           1   0.058   0.000  uart__n0032<2>cy (uart__n0032<2>_cyo)
     MUXCY:CI->O           1   0.058   0.000  uart__n0032<3>cy (uart__n0032<3>_cyo)
     MUXCY:CI->O           1   0.058   0.000  uart__n0032<4>cy (uart__n0032<4>_cyo)
     MUXCY:CI->O           1   0.058   0.000  uart__n0032<5>cy (uart__n0032<5>_cyo)
     MUXCY:CI->O           1   0.058   0.000  uart__n0032<6>cy (uart__n0032<6>_cyo)
     MUXCY:CI->O           1   0.058   0.000  uart__n0032<7>cy (uart__n0032<7>_cyo)
     MUXCY:CI->O           1   0.058   0.000  uart__n0032<8>cy (uart__n0032<8>_cyo)
     MUXCY:CI->O           1   0.058   0.000  uart__n0032<9>cy (uart__n0032<9>_cyo)
     MUXCY:CI->O           1   0.058   0.000  uart__n0032<10>cy (uart__n0032<10>_cyo)
     MUXCY:CI->O           0   0.058   0.000  uart__n0032<11>cy (uart__n0032<11>_cyo)
     XORCY:CI->O           4   0.648   1.520  uart__n0032<12>_xor (_n0032<12>)
     INV:I->O              1   0.468   0.000  norlut3_INV_0 (N14)
     MUXCY:S->O            2   0.515   1.150  norcy_rn_2 (nor_cyo3)
     LUT3:I2->O           13   0.468   2.550  _n00191 (_n0019)
     FDR:R                     0.577          c_0
    ----------------------------------------
    Total                     11.659ns (5.289ns logic, 6.370ns route)
                                       (45.4% logic, 54.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'bclk:Q'
  Clock period: 5.422ns (frequency: 184.434MHz)
  Total number of paths / destination ports: 27 / 6
-------------------------------------------------------------------------
Delay:               5.422ns (Levels of Logic = 2)
  Source:            current_state_FFd1 (FF)
  Destination:       cnt_1 (FF)
  Source Clock:      bclk:Q rising
  Destination Clock: bclk:Q rising

  Data Path: current_state_FFd1 to cnt_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              6   0.992   1.850  current_state_FFd1 (current_state_FFd1)
     LUT2:I1->O            1   0.468   0.920  _n0014<1>1_SW0 (N91)
     LUT4:I1->O            1   0.468   0.000  _n0014<1>1 (_n0014<1>)
     FDE:D                     0.724          cnt_1
    ----------------------------------------
    Total                      5.422ns (2.652ns logic, 2.770ns route)
                                       (48.9% logic, 51.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'bclk:Q'
  Total number of paths / destination ports: 33 / 9
-------------------------------------------------------------------------
Offset:              6.110ns (Levels of Logic = 3)
  Source:            en<2> (PAD)
  Destination:       txd (FF)
  Destination Clock: bclk:Q rising

  Data Path: en<2> to txd
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.797   0.920  en_2_IBUF (en_2_IBUF)
     LUT4:I0->O            1   0.468   0.920  _n00061 (N41)
     LUT2:I1->O            6   0.468   1.850  _n00062 (_n0006)
     FDE:CE                    0.687          txd
    ----------------------------------------
    Total                      6.110ns (2.420ns logic, 3.690ns route)
                                       (39.6% logic, 60.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'tclk:Q'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              2.441ns (Levels of Logic = 1)
  Source:            tre (PAD)
  Destination:       reg_tre (FF)
  Destination Clock: tclk:Q rising

  Data Path: tre to reg_tre
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.797   0.920  tre_IBUF (tre_IBUF)
     FD:D                      0.724          reg_tre
    ----------------------------------------
    Total                      2.441ns (1.521ns logic, 0.920ns route)
                                       (62.3% logic, 37.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'bclk:Q'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.514ns (Levels of Logic = 1)
  Source:            txd (FF)
  Destination:       txd (PAD)
  Source Clock:      bclk:Q rising

  Data Path: txd to txd
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   0.992   0.920  txd (txd_OBUF)
     OBUF:I->O                 4.602          txd_OBUF (txd)
    ----------------------------------------
    Total                      6.514ns (5.594ns logic, 0.920ns route)
                                       (85.9% logic, 14.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              6.514ns (Levels of Logic = 1)
  Source:            dout_7 (FF)
  Destination:       dout<7> (PAD)
  Source Clock:      clk falling

  Data Path: dout_7 to dout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE_1:C->Q            1   0.992   0.920  dout_7 (dout_7)
     OBUF:I->O                 4.602          dout_7_OBUF (dout<7>)
    ----------------------------------------
    Total                      6.514ns (5.594ns logic, 0.920ns route)
                                       (85.9% logic, 14.1% route)

=========================================================================
CPU : 15.25 / 16.47 s | Elapsed : 15.00 / 16.00 s
 
--> 

Total memory usage is 88484 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    4 (   0 filtered)