page_step.syr

总体演示程序DEMO_FPGA.rar

Release 7.1.01i - xst H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: page_step.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "page_step.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "page_step"
Output Format                      : NGC
Target Device                      : xc2s100e-6-pq208

---- Source Options
Top Module Name                    : page_step
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : page_step.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/DEMO_FPGA/page_step.vhd" in Library work.
Entity <page_step> compiled.
Entity <page_step> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <page_step> (Architecture <behavioral>).
Entity <page_step> analyzed. Unit <page_step> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <page_step>.
    Related source file is "E:/DEMO_FPGA/page_step.vhd".
INFO:Xst:1799 - State st5 is never reached in FSM <current_state>.
INFO:Xst:1799 - State st6 is never reached in FSM <current_state>.
    Found finite state machine <FSM_0> for signal <current_state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 9                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | ireset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | st0                                            |
    | Power Up State     | st0                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 5-bit addsub for signal <$n0003> created at line 51.
    Found 5-bit comparator less for signal <$n0005> created at line 63.
    Found 5-bit comparator greater for signal <$n0006> created at line 73.
    Found 5-bit register for signal <c>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   5 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   2 Comparator(s).
Unit <page_step> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <current_state[1:3]> with gray encoding.
-------------------
 State | Encoding
-------------------
 st0   | 000
 st1   | 011
 st2   | 010
 st3   | 001
 st4   | 110
 st5   | unreached
 st6   | unreached
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 1
 5-bit addsub                      : 1
# Registers                        : 4
 1-bit register                    : 3
 5-bit register                    : 1
# Comparators                      : 2
 5-bit comparator greater          : 1
 5-bit comparator less             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <page_step> ...
Loading device for application Rf_Device from file '2s100e.nph' in environment E:/Program/EDA/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block page_step, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : page_step.ngr
Top Level Output File Name         : page_step
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 9

Macro Statistics :
# Registers                        : 1
#      5-bit register              : 1
# Adders/Subtractors               : 1
#      5-bit addsub                : 1
# Comparators                      : 2
#      5-bit comparator greater    : 1
#      5-bit comparator less       : 1

Cell Usage :
# BELS                             : 36
#      LUT2                        : 1
#      LUT2_L                      : 1
#      LUT3                        : 4
#      LUT3_L                      : 5
#      LUT4                        : 2
#      LUT4_D                      : 1
#      LUT4_L                      : 12
#      MUXCY                       : 4
#      MUXF5                       : 1
#      XORCY                       : 5
# FlipFlops/Latches                : 8
#      FDC                         : 8
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 8
#      IBUF                        : 3
#      OBUF                        : 5
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100epq208-6 

 Number of Slices:                      14  out of   1200     1%  
 Number of Slice Flip Flops:             8  out of   2400     0%  
 Number of 4 input LUTs:                26  out of   2400     1%  
 Number of bonded IOBs:                  9  out of    146     6%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 8     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.322ns (Maximum Frequency: 120.163MHz)
   Minimum input arrival time before clock: 3.877ns
   Maximum output required time after clock: 7.544ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 8.322ns (frequency: 120.163MHz)
  Total number of paths / destination ports: 142 / 8
-------------------------------------------------------------------------
Delay:               8.322ns (Levels of Logic = 7)
  Source:            current_state_FFd3 (FF)
  Destination:       c_4 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: current_state_FFd3 to c_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             19   0.992   2.950  current_state_FFd3 (current_state_FFd3)
     LUT2:I1->O            1   0.468   0.920  _n00041 (_n0004)
     MUXCY:CI->O           1   0.058   0.000  page_step__n0003<0>cy (page_step__n0003<0>_cyo)
     MUXCY:CI->O           1   0.058   0.000  page_step__n0003<1>cy (page_step__n0003<1>_cyo)
     MUXCY:CI->O           1   0.058   0.000  page_step__n0003<2>cy (page_step__n0003<2>_cyo)
     MUXCY:CI->O           0   0.058   0.000  page_step__n0003<3>cy (page_step__n0003<3>_cyo)
     XORCY:CI->O           1   0.648   0.920  page_step__n0003<4>_xor (_n0003<4>)
     LUT4_L:I0->LO         1   0.468   0.000  _n0002<4>46 (_n0002<4>)
     FDC:D                     0.724          c_4
    ----------------------------------------
    Total                      8.322ns (3.532ns logic, 4.790ns route)
                                       (42.4% logic, 57.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 5 / 3
-------------------------------------------------------------------------
Offset:              3.877ns (Levels of Logic = 3)
  Source:            ibuttonb (PAD)
  Destination:       current_state_FFd2 (FF)
  Destination Clock: clk rising

  Data Path: ibuttonb to current_state_FFd2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   0.797   1.320  ibuttonb_IBUF (ibuttonb_IBUF)
     LUT4_L:I1->LO         1   0.468   0.100  current_state_FFd2-In1 (N10)
     LUT2_L:I1->LO         1   0.468   0.000  current_state_FFd2-In2 (current_state_FFd2-In)
     FDC:D                     0.724          current_state_FFd2
    ----------------------------------------
    Total                      3.877ns (2.457ns logic, 1.420ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 5 / 5
-------------------------------------------------------------------------
Offset:              7.544ns (Levels of Logic = 1)
  Source:            c_4 (FF)
  Destination:       data<4> (PAD)
  Source Clock:      clk rising

  Data Path: c_4 to data<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              7   0.992   1.950  c_4 (c_4)
     OBUF:I->O                 4.602          data_4_OBUF (data<4>)
    ----------------------------------------
    Total                      7.544ns (5.594ns logic, 1.950ns route)
                                       (74.2% logic, 25.8% route)

=========================================================================
CPU : 10.96 / 11.83 s | Elapsed : 11.00 / 11.00 s
 
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Total memory usage is 87460 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    3 (   0 filtered)