lcd.syr

总体演示程序DEMO_FPGA.rar

Loading device for application Rf_Device from file '2s100e.nph' in environment E:/Program/EDA/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lcd, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : lcd.ngr
Top Level Output File Name         : lcd
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 26

Macro Statistics :
# Registers                        : 4
#      1-bit register              : 1
#      5-bit register              : 2
#      8-bit register              : 1
# Adders/Subtractors               : 1
#      5-bit adder                 : 1

Cell Usage :
# BELS                             : 48
#      GND                         : 1
#      INV                         : 2
#      LUT1_L                      : 4
#      LUT2                        : 1
#      LUT3                        : 1
#      LUT3_L                      : 4
#      LUT4                        : 1
#      LUT4_D                      : 5
#      LUT4_L                      : 20
#      MUXCY                       : 4
#      VCC                         : 1
#      XORCY                       : 4
# FlipFlops/Latches                : 27
#      FDC_1                       : 12
#      FDE_1                       : 14
#      FDP_1                       : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 25
#      IBUF                        : 9
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100epq208-6 

 Number of Slices:                      24  out of   1200     2%  
 Number of Slice Flip Flops:            27  out of   2400     1%  
 Number of 4 input LUTs:                36  out of   2400     1%  
 Number of bonded IOBs:                 26  out of    146    17%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 27    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.559ns (Maximum Frequency: 116.836MHz)
   Minimum input arrival time before clock: 7.252ns
   Maximum output required time after clock: 6.744ns
   Maximum combinational path delay: 8.465ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 8.559ns (frequency: 116.836MHz)
  Total number of paths / destination ports: 241 / 26
-------------------------------------------------------------------------
Delay:               8.559ns (Levels of Logic = 7)
  Source:            cnt2_0 (FF)
  Destination:       current_state_FFd6 (FF)
  Source Clock:      clk falling
  Destination Clock: clk falling

  Data Path: cnt2_0 to current_state_FFd6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            5   0.992   1.720  cnt2_0 (cnt2_0)
     INV:I->O              1   0.468   0.000  lcd__n0013<0>lut_INV_0 (N3)
     MUXCY:S->O            1   0.515   0.000  lcd__n0013<0>cy (lcd__n0013<0>_cyo)
     MUXCY:CI->O           1   0.058   0.000  lcd__n0013<1>cy (lcd__n0013<1>_cyo)
     MUXCY:CI->O           1   0.058   0.000  lcd__n0013<2>cy (lcd__n0013<2>_cyo)
     XORCY:CI->O           4   0.648   1.520  lcd__n0013<3>_xor (_n0013<3>)
     LUT4_D:I3->O          1   0.468   0.920  current_state_FFd8-In2_SW0 (N26)
     LUT4_L:I1->LO         1   0.468   0.000  current_state_FFd6-In2 (current_state_FFd6-In)
     FDC_1:D                   0.724          current_state_FFd6
    ----------------------------------------
    Total                      8.559ns (4.399ns logic, 4.160ns route)
                                       (51.4% logic, 48.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 22 / 22
-------------------------------------------------------------------------
Offset:              7.252ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       lcd_address_4 (FF)
  Destination Clock: clk falling

  Data Path: reset to lcd_address_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            14   0.797   2.650  reset_IBUF (reset_IBUF)
     INV:I->O             14   0.468   2.650  lcd_address_N01_INV_0 (lcd_address_N0)
     FDE_1:CE                  0.687          lcd_address_0
    ----------------------------------------
    Total                      7.252ns (1.952ns logic, 5.300ns route)
                                       (26.9% logic, 73.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset:              6.744ns (Levels of Logic = 1)
  Source:            lcdda (FF)
  Destination:       lcdda (PAD)
  Source Clock:      clk falling

  Data Path: lcdda to lcdda
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE_1:C->Q            2   0.992   1.150  lcdda (lcdda_OBUF)
     OBUF:I->O                 4.602          lcdda_OBUF (lcdda)
    ----------------------------------------
    Total                      6.744ns (5.594ns logic, 1.150ns route)
                                       (82.9% logic, 17.1% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               8.465ns (Levels of Logic = 2)
  Source:            clk (PAD)
  Destination:       lcden (PAD)

  Data Path: clk to lcden
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O           28   0.663   3.200  clk_BUFGP (lcden_OBUF)
     OBUF:I->O                 4.602          lcden_OBUF (lcden)
    ----------------------------------------
    Total                      8.465ns (5.265ns logic, 3.200ns route)
                                       (62.2% logic, 37.8% route)

=========================================================================
CPU : 11.83 / 12.66 s | Elapsed : 12.00 / 13.00 s
 
--> 

Total memory usage is 87460 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    4 (   0 filtered)