lcd.syr

总体演示程序DEMO_FPGA.rar

Release 7.1.01i - xst H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: lcd.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "lcd.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "lcd"
Output Format                      : NGC
Target Device                      : xc2s100e-6-pq208

---- Source Options
Top Module Name                    : lcd
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : lcd.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/DEMO_FPGA/lcd_driver.vhd" in Library work.
Entity <lcd> compiled.
Entity <lcd> (Architecture <driver>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <lcd> (Architecture <driver>).
Entity <lcd> analyzed. Unit <lcd> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lcd>.
    Related source file is "E:/DEMO_FPGA/lcd_driver.vhd".
INFO:Xst:1799 - State write_data3 is never reached in FSM <current_state>.
INFO:Xst:1799 - State set_location2 is never reached in FSM <current_state>.
INFO:Xst:1799 - State set_cgram_location is never reached in FSM <current_state>.
INFO:Xst:1799 - State write_cgram is never reached in FSM <current_state>.
    Found finite state machine <FSM_0> for signal <current_state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 10                                             |
    | Inputs             | 2                                              |
    | Outputs            | 8                                              |
    | Clock              | clk (falling_edge)                             |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | set_dlnf                                       |
    | Power Up State     | set_dlnf                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <lcdda>.
    Found 5-bit register for signal <lcd_address>.
    Found 8-bit register for signal <data>.
    Found 5-bit adder for signal <$n0013> created at line 63.
    Found 5-bit register for signal <cnt2>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  19 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <lcd> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <current_state[1:8]> with speed1 encoding.
--------------------------------
 State              | Encoding
--------------------------------
 set_dlnf           | 10000000
 clear_lcd          | 01000000
 set_cursor         | 00100000
 set_location3      | 00000001
 write_data2        | 00010000
 set_dcb            | 00001000
 set_location       | 00000100
 write_data         | 00000010
 write_data3        | unreached
 set_location2      | unreached
 set_cgram_location | unreached
 write_cgram        | unreached
--------------------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 1
 5-bit adder                       : 1
# Registers                        : 12
 1-bit register                    : 9
 5-bit register                    : 2
 8-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <lcd> ...