entity.cpp

总体演示程序DEMO_FPGA.rar

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /___/   /      
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////


#include "simprim.auxlib/vpackage/vpackage.h"
#include "simprim.auxlib/vcomponents/vcomponents.h"
#include "ieee/std_logic_1164/std_logic_1164.h"
#include "work/digital_clk/entity.h"

static const char *entFileName = "E:/DEMO_FPGA/digital_clk_timesim.vhd";
#ifdef _MSC_VER
#pragma warning(disable: 4355)
#endif

Work_digital_clk::Work_digital_clk(const char *name, const char* ArchName, const char* fileName, int numOfLine): HSim__s6(false,name,"digital_clk", ArchName, fileName, HSim::VhdlDesignEntity, numOfLine + 9)

{
  SE[0].initialize("clk", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigIn, HSimSA::charToMem(1));
  ;
  ;
  SE[1].initialize("ireset", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigIn, HSimSA::charToMem(1));
  ;
  ;
  SE[2].initialize("oh", &IeeeStd_logic_1164->Std_logic_vector, MKConstr(7, 0, HSim::DOWNTO), this, HSim::PortSigOut, (const char*)0);
  ;
  SE[2].setDefaultValue((char *)0);
;
  SE[3].initialize("om", &IeeeStd_logic_1164->Std_logic_vector, MKConstr(7, 0, HSim::DOWNTO), this, HSim::PortSigOut, (const char*)0);
  ;
  SE[3].setDefaultValue((char *)0);
;
  SE[4].initialize("os", &IeeeStd_logic_1164->Std_logic_vector, MKConstr(7, 0, HSim::DOWNTO), this, HSim::PortSigOut, (const char*)0);
  ;
  SE[4].setDefaultValue((char *)0);
;
  SetPorts();
 
}

Work_digital_clk::~Work_digital_clk()
{
}

void Work_digital_clk::SetPorts()
{
}

void Work_digital_clk::constructEntityObject()
{
;
}