electronic_organ.syr

总体演示程序DEMO_FPGA.rar

Design Statistics
# IOs                              : 6

Macro Statistics :
# Registers                        : 1
#      1-bit register              : 1
# Counters                         : 1
#      18-bit up counter           : 1
# Adders/Subtractors               : 1
#      18-bit adder                : 1
# Comparators                      : 4
#      18-bit comparator less      : 4

Cell Usage :
# BELS                             : 191
#      GND                         : 1
#      INV                         : 4
#      LUT1_L                      : 17
#      LUT2                        : 2
#      LUT2_L                      : 32
#      LUT3                        : 1
#      LUT3_L                      : 17
#      LUT4                        : 11
#      MUXCY                       : 70
#      VCC                         : 1
#      XORCY                       : 35
# FlipFlops/Latches                : 19
#      FDRSE                       : 18
#      FDSE                        : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 5
#      IBUF                        : 4
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100epq208-6 

 Number of Slices:                      53  out of   1200     4%  
 Number of Slice Flip Flops:            19  out of   2400     0%  
 Number of 4 input LUTs:                80  out of   2400     3%  
 Number of bonded IOBs:                  6  out of    146     4%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 19    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 12.269ns (Maximum Frequency: 81.506MHz)
   Minimum input arrival time before clock: 12.946ns
   Maximum output required time after clock: 6.514ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 12.269ns (frequency: 81.506MHz)
  Total number of paths / destination ports: 13590 / 38
-------------------------------------------------------------------------
Delay:               12.269ns (Levels of Logic = 22)
  Source:            cnt_0 (FF)
  Destination:       cnt_11 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: cnt_0 to cnt_11
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRSE:C->Q            2   0.992   1.150  cnt_0 (cnt_0)
     INV:I->O              2   0.468   0.000  electronic_organ__n0009<0>lut_INV_0 (N3)
     MUXCY:S->O            1   0.515   0.000  electronic_organ__n0009<0>cy (electronic_organ__n0009<0>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<1>cy (electronic_organ__n0009<1>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<2>cy (electronic_organ__n0009<2>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<3>cy (electronic_organ__n0009<3>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<4>cy (electronic_organ__n0009<4>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<5>cy (electronic_organ__n0009<5>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<6>cy (electronic_organ__n0009<6>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<7>cy (electronic_organ__n0009<7>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<8>cy (electronic_organ__n0009<8>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<9>cy (electronic_organ__n0009<9>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<10>cy (electronic_organ__n0009<10>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<11>cy (electronic_organ__n0009<11>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<12>cy (electronic_organ__n0009<12>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<13>cy (electronic_organ__n0009<13>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<14>cy (electronic_organ__n0009<14>_cyo)
     MUXCY:CI->O           1   0.058   0.000  electronic_organ__n0009<15>cy (electronic_organ__n0009<15>_cyo)
     MUXCY:CI->O           0   0.058   0.000  electronic_organ__n0009<16>cy (electronic_organ__n0009<16>_cyo)
     XORCY:CI->O           3   0.648   1.320  electronic_organ__n0009<17>_xor (_n0009<17>)
     INV:I->O              1   0.468   0.000  norlut1_INV_0 (N21)
     MUXCY:S->O            3   0.515   1.320  norcy_rn_0 (nor_cyo1)
     LUT3:I0->O           18   0.468   2.900  _n00042 (_n0004)
     FDRSE:R                   0.577          cnt_0
    ----------------------------------------
    Total                     12.269ns (5.579ns logic, 6.690ns route)
                                       (45.5% logic, 54.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 3328 / 39
-------------------------------------------------------------------------
Offset:              12.946ns (Levels of Logic = 6)
  Source:            button<0> (PAD)
  Destination:       cnt_11 (FF)
  Destination Clock: clk rising

  Data Path: button<0> to cnt_11
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            11   0.797   2.350  button_0_IBUF (button_0_IBUF)
     LUT4:I0->O           21   0.468   3.025  div_cnt<17>1 (div_cnt<17>)
     LUT2_L:I1->LO         1   0.468   0.000  XNor_stagelut15 (N20)
     MUXCY:S->O            1   0.515   0.000  XNor_stagecy_rn_14 (XNor_stage_cyo15)
     MUXCY:CI->O           3   0.058   1.320  norcy_rn_0 (nor_cyo1)
     LUT3:I0->O           18   0.468   2.900  _n00042 (_n0004)
     FDRSE:R                   0.577          cnt_0
    ----------------------------------------
    Total                     12.946ns (3.351ns logic, 9.595ns route)
                                       (25.9% logic, 74.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.514ns (Levels of Logic = 1)
  Source:            tone (FF)
  Destination:       tone (PAD)
  Source Clock:      clk rising

  Data Path: tone to tone
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDSE:C->Q             1   0.992   0.920  tone (tone_OBUF)
     OBUF:I->O                 4.602          tone_OBUF (tone)
    ----------------------------------------
    Total                      6.514ns (5.594ns logic, 0.920ns route)
                                       (85.9% logic, 14.1% route)

=========================================================================
CPU : 27.73 / 36.00 s | Elapsed : 28.00 / 31.00 s
 
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Total memory usage is 88484 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    0 (   0 filtered)