untitled1.v

总体演示程序DEMO_FPGA.rar

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-- Company: 
-- Engineer:
--
-- Create Date:    22:11:32 03/24/05
-- Design Name:    
-- Module Name:    page_step - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity page_step is
    Port ( clk : in std_logic;    --1khz
           ireset   : in std_logic;
           ibuttona : in std_logic;
		 ibuttonb	: in std_logic;
           data :out std_logic_vector(4 downto 0));
end page_step;

architecture Behavioral of page_step is

type state is (st0,st1,st2,st3,st4,st5,st6);
signal current_state : state;

begin
process(clk,ireset)
variable c : std_logic_vector(4 downto 0);
begin
   if ireset='1' then 
      c:="00000";
	 current_state<=st0;
   elsif rising_edge(clk) then
      case current_state is
	 when st0=>
	         if ibuttona='1' then
		       current_state<=st1;
              end if;

		    if ibuttonb='1' then
		       current_state<=st3;
              end if;

       when st1=>
	            current_state<=st2;
	         if c<"00100" then c:=c+1;
		    end if;

	  when st2=>
	         if ibuttona='0' then
		       current_state<=st0;
              end if;
       -----------------------------------
	  when st3=>
	            current_state<=st4;
		    if c>"00001" then c:=c-1;
  		    end if;

       when st4=>
	         if ibuttonb='0' then
	            current_state<=st0;
		    end if;
       -----------------------------------
	  when others=>
	            current_state<=st0;
	  end case;
    end if;

    data<=c;
end process;
end Behavioral;