mem_infor.xco

总体演示程序DEMO_FPGA.rar

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = e:\demo_fpga\tmp
SET speedgrade = -6
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
# SET outputdirectory = E:\DEMO_FPGA\
SET device = xc2s100e
# SET projectname = coregen
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = pq208
SET createndf = False
SET designentry = VHDL
SET devicefamily = spartan2e
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.1
# END Select
# BEGIN Parameters
CSET handshaking_pins=false
CSET init_value=0
CSET coefficient_file=E:\DEMO_FPGA\bkram_demo_fpga\bk1_demo_fpga.coe
CSET select_primitive=512x8
CSET initialization_pin_polarity=Active_High
CSET global_init_value=0
CSET depth=1024
CSET write_enable_polarity=Active_High
CSET port_configuration=Read_Only
CSET enable_pin_polarity=Active_High
CSET component_name=mem_infor
CSET active_clock_edge=Rising_Edge_Triggered
CSET additional_output_pipe_stages=0
CSET disable_warning_messages=true
CSET limit_data_pitch=8
CSET primitive_selection=Select_Primitive
CSET enable_pin=false
CSET init_pin=false
CSET write_mode=Read_After_Write
CSET has_limit_data_pitch=false
CSET load_init_file=true
CSET width=8
CSET register_inputs=false
# END Parameters
GENERATE