digital_voltmeter.twr

总体演示程序DEMO_FPGA.rar

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Release 7.1.01i Trace H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

E:/Program/EDA/Xilinx/bin/nt/trce.exe -ise e:\demo_fpga\DEMO_FPGA.ise -intstyle
ise -e 3 -l 3 -s 6 -xml digital_voltmeter digital_voltmeter.ncd -o
digital_voltmeter.twr digital_voltmeter.pcf


Design file:              digital_voltmeter.ncd
Physical constraint file: digital_voltmeter.pcf
Device,speed:             xc2s100e,-6 (PRODUCTION 1.18 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    6.946|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Thu Mar 24 23:25:55 2005
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Peak Memory Usage: 71 MB