📄 uart.twr
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Release 7.1.01i Trace H.39
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
E:/Program/EDA/Xilinx/bin/nt/trce.exe -ise e:\demo_fpga\DEMO_FPGA.ise -intstyle
ise -e 3 -l 3 -s 6 -xml uart uart.ncd -o uart.twr uart.pcf
Design file: uart.ncd
Physical constraint file: uart.pcf
Device,speed: xc2s100e,-6 (PRODUCTION 1.18 2005-01-22)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
dout<0> | 6.460(F)|clk_BUFGP | 0.000|
dout<1> | 6.452(F)|clk_BUFGP | 0.000|
dout<2> | 6.460(F)|clk_BUFGP | 0.000|
dout<3> | 6.452(F)|clk_BUFGP | 0.000|
dout<4> | 6.460(F)|clk_BUFGP | 0.000|
dout<5> | 6.436(F)|clk_BUFGP | 0.000|
dout<6> | 6.460(F)|clk_BUFGP | 0.000|
dout<7> | 6.436(F)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 10.483| | | 5.721|
---------------+---------+---------+---------+---------+
Analysis completed Fri Mar 25 09:04:08 2005
--------------------------------------------------------------------------------
Peak Memory Usage: 70 MB
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