keyboards.vhd

总体演示程序DEMO_FPGA.rar

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-- Company: 
-- Engineer:
--
-- Create Date:    17:55:50 03/24/05
-- Design Name:    
-- Module Name:    keyboards - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity keyboards is
    Port ( clk : in std_logic;
           ienter : in std_logic;
           istepa : in std_logic;
           istepb : in std_logic;
           ichose : in std_logic;
           ireset : in std_logic;
		 -----------------------
           oenter : out std_logic;
           ostepa : out std_logic;
           ostepb : out std_logic;
           ochose : out std_logic;
           oreset : out std_logic);
end keyboards;

architecture Behavioral of keyboards is
component button1 is
    Port ( clk : in std_logic;
           ibutton : in std_logic;
           obutton :out std_logic);
end component;

begin
u0 : button1 port map(clk=>clk,ibutton=>ienter,obutton=>oenter);
u1 : button1 port map(clk=>clk,ibutton=>istepa,obutton=>ostepa);
u2 : button1 port map(clk=>clk,ibutton=>istepb,obutton=>ostepb);
u3 : button1 port map(clk=>clk,ibutton=>ichose,obutton=>ochose);
u4 : button1 port map(clk=>clk,ibutton=>ireset,obutton=>oreset);

end Behavioral;