demo_all.par

总体演示程序DEMO_FPGA.rar

Release 7.1.01i par H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

HXS::  Sun Apr 03 23:21:23 2005

par -w -intstyle ise -ol std -t 1 demo_all_map.ncd demo_all.ncd demo_all.pcf 


Constraints file: demo_all.pcf.
Loading device for application Rf_Device from file '2s100e.nph' in environment
E:/Program/EDA/Xilinx.
   "demo_all" is an NCD, version 3.1, device xc2s100e, package pq208, speed -6

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 85.000
Celsius)
Initializing voltage to 1.700 Volts. (default - Range: 1.700 to 1.900 Volts)


Device speed data version:  "PRODUCTION 1.18 2005-01-22".


Device Utilization Summary:

   Number of BLOCKRAMs                 3 out of 10     30%
   Number of GCLKs                     4 out of 4     100%
   Number of External GCLKIOBs         1 out of 4      25%
      Number of LOCed GCLKIOBs         1 out of 1     100%

   Number of External IOBs            46 out of 142    32%
      Number of LOCed IOBs            46 out of 46    100%

   Number of SLICEs                 1032 out of 1200   86%


Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98c35f) REAL time: 4 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 4 secs 

Phase 3.23
Phase 3.23 (Checksum:1c9c37d) REAL time: 4 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 4 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 4 secs 

Phase 6.8
................................................................................................
Phase 6.8 (Checksum:c43e8d) REAL time: 10 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 10 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 13 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 13 secs 

Writing design to file demo_all.ncd


Total REAL time to Placer completion: 14 secs 
Total CPU time to Placer completion: 11 secs 

Starting Router

Phase 1: 6175 unrouted;       REAL time: 15 secs 

Phase 2: 5642 unrouted;       REAL time: 22 secs 

Phase 3: 1467 unrouted;       REAL time: 26 secs 

Phase 4: 0 unrouted;       REAL time: 30 secs 

Total REAL time to Router completion: 30 secs 
Total CPU time to Router completion: 26 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|            u4/clk1k |      GCLKBUF3| No   |   67 |  0.279     |  0.564      |
+---------------------+--------------+------+------+------------+-------------+
|        u4/reg_clk1k |      GCLKBUF2| No   |   80 |  0.141     |  0.513      |
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      GCLKBUF0| No   |  124 |  0.066     |  0.416      |
+---------------------+--------------+------+------+------------+-------------+
|            u0/clk1m |      GCLKBUF1| No   |   63 |  0.060     |  0.411      |
+---------------------+--------------+------+------+------------+-------------+
|        u1/u3/PreCLK |      Low-Skew|      |    9 |  0.194     |  3.926      |
+---------------------+--------------+------+------+------------+-------------+
|        u1/u2/_n0003 |      Low-Skew|      |    6 |  0.209     |  4.247      |
+---------------------+--------------+------+------+------------+-------------+
|            u3/clk10 |      Low-Skew|      |   26 |  0.577     |  4.654      |
+---------------------+--------------+------+------+------------+-------------+
|     u4/u5/u0/_n0001 |      Low-Skew|      |    8 |  0.253     |  5.493      |
+---------------------+--------------+------+------+------------+-------------+
|        u1/u1/_n0002 |      Low-Skew|      |    3 |  0.096     |  4.800      |
+---------------------+--------------+------+------+------------+-------------+
|      u4/u4/u0/sclka |      Low-Skew|      |    5 |  0.117     |  4.215      |
+---------------------+--------------+------+------+------------+-------------+
|     u1/u0/clk_12MHz |         Local|      |    2 |  0.097     |  3.179      |
+---------------------+--------------+------+------+------------+-------------+
|           u3/button |         Local|      |    5 |  0.493     |  3.807      |
+---------------------+--------------+------+------+------------+-------------+
|        u4/u8/_n0001 |         Local|      |    7 |  2.683     |  3.837      |
+---------------------+--------------+------+------+------------+-------------+
|              _n0124 |         Local|      |    8 |  2.887     |  3.706      |
+---------------------+--------------+------+------+------------+-------------+
|            u2/clk1k |         Local|      |   11 |  0.919     |  3.277      |
+---------------------+--------------+------+------+------------+-------------+
|             u2/clk1 |         Local|      |   17 |  1.535     |  3.493      |
+---------------------+--------------+------+------+------------+-------------+
|              _n0002 |         Local|      |   17 |  1.277     |  3.908      |
+---------------------+--------------+------+------+------------+-------------+
|           u2/button |         Local|      |   13 |  0.326     |  3.631      |
+---------------------+--------------+------+------+------------+-------------+
|       u1/u0/clk_8Hz |         Local|      |    4 |  0.059     |  3.160      |
+---------------------+--------------+------+------+------------+-------------+
|             u4/clk1 |         Local|      |    6 |  1.689     |  3.127      |
+---------------------+--------------+------+------+------------+-------------+
|              _n0123 |         Local|      |   11 |  0.000     |  3.836      |
+---------------------+--------------+------+------+------------+-------------+
|     u4/u4/u1/_n0001 |         Local|      |    5 |  0.040     |  3.673      |
+---------------------+--------------+------+------+------------+-------------+
|      u1/u3/FullSpkS |         Local|      |    1 |  0.000     |  0.531      |
+---------------------+--------------+------+------+------------+-------------+
|      u4/u4/u0/sclkb |         Local|      |    6 |  2.809     |  3.652      |
+---------------------+--------------+------+------+------------+-------------+
|              _n0003 |         Local|      |    5 |  0.171     |  3.698      |
+---------------------+--------------+------+------+------------+-------------+
|              _n0125 |         Local|      |    1 |  0.000     |  2.443      |
+---------------------+--------------+------+------+------------+-------------+
|              _n0122 |         Local|      |   10 |  2.119     |  4.071      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 33 secs 
Total CPU time to PAR completion: 28 secs 

Peak Memory Usage:  84 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file demo_all.ncd



PAR done!