page4.vhd

总体演示程序DEMO_FPGA.rar

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    03:53:52 03/25/05
-- Design Name:    
-- Module Name:    page4 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity page4 is
    Port ( en : in std_logic_vector(4 downto 0);
           addr: in std_logic_vector(4 downto 0);            
           din : in std_logic_vector(7 downto 0);
           dint : in std_logic_vector(23 downto 0);
           dout : out std_logic_vector(7 downto 0));
end page4;

architecture Behavioral of page4 is

begin

process(en,din,addr)
begin
   if en="10100" then
      case addr is
	 when "11000"=>
	             dout<="0011"&dint(23 downto 20);
	 when "11001"=>
	             dout<="0011"&dint(19 downto 16);

	 when "11010"=>
	             dout<="0011"&dint(15 downto 12);
	 when "11011"=>
	             dout<="0011"&dint(11 downto 8);

	 when "11100"=>
	             dout<="0011"&dint(7 downto 4);
	 when "11101"=>
	             dout<="0011"&dint(3 downto 0);
	 when others=>
	             dout<=din;
	 end case;
   end if;
end process;	 

end Behavioral;