plb_tft_cntlr_ref.v

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//-----------------------------------------------------------------------------
// TFT Controller - Top Level Module
//-----------------------------------------------------------------------------
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//     
//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
// 
//----------------------------------------------------------------------------
// Filename:     tft_top.v
// 
// Description:    
//
// Design Notes:
//   
//-----------------------------------------------------------------------------
// Structure:   
// 
//   -- plb_tft_cntlr.v
//      -- dcr_if.v
//      -- plb_if.v  
//        -- trans_control.v
//        -- color_control.v
//        -- line_control.v
//        -- pixel_control.v
//        -- plb_xfer_control.v
//      -- h_sync.v
//      -- v_sync.v
//      -- RGB_BRAM.v
//      -- tft_if.v                
//
//-----------------------------------------------------------------------------
// Author:    CJN
// History:
//   CJN
//
//-----------------------------------------------------------------------------

///////////////////////////////////////////////////////////////////////////////
// Module Declaration
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 100 ps
module plb_tft_cntlr_ref (

  // PLB GLOBAL SIGNALS
  SYS_plbClk,        // I  100MHz
  SYS_plbReset,      // I 

  // REQUEST QUALIFIERS INPUTS
  PLB_MnAddrAck,     // I
  PLB_MnRearbitrate, // I
  PLB_Mnssize,       // I [0:1]
  PLB_MnBusy,        // I
  PLB_MnErr,         // I
  PLB_pendReq,       // I
  PLB_pendPri,       // I [0:1]
  PLB_reqPri,        // I [0:1]    
  Mn_request,        // O
  Mn_priority,       // O [0:1]
  Mn_busLock,        // O 
  Mn_RNW,            // O
  Mn_BE,             // O [0:7]
  Mn_size,           // O [0:3]
  Mn_type,           // O [0:2]

  Mn_msize,          // O [0:1]          
  Mn_compress,       // O        
  Mn_guarded,        // O
  Mn_lockErr,        // O
  Mn_ordered,        // O
  Mn_abort,          // O
  Mn_ABus,           // O [0:31]

  // PLB WRITE DATA BUS
  PLB_MnWrDAck,      // I       
  PLB_MnWrBTerm,     // I
  Mn_wrBurst,        // O
  Mn_wrDBus,         // O [0:63]

  // PLB READ DATA BUS              
  PLB_MnRdDAck,      // I
  PLB_MnRdBTerm,     // I
  PLB_MnRdWdAddr,    // I [0:3]
  PLB_MnRdDBus,      // I [0:63]       
  Mn_rdBurst,        // O


  // DCR BUS
  SYS_dcrClk,        // I
  DCR_ABus,          // I [0:9]
  DCR_DBusIn,        // I [0:31]
  DCR_Read,          // I
  DCR_Write,         // I
  DCR_Ack,           // O
  DCR_DBusOut,       // O [0:31]
  
  // TFT SIGNALS OUT TO HW
  SYS_tftClk,        // I
  TFT_LCD_HSYNC,     // O    
  TFT_LCD_VSYNC,     // O
  TFT_LCD_DE,        // O
  TFT_LCD_CLK,       // O
  TFT_LCD_DPS,       // O
  TFT_LCD_R,         // O [5:0]
  TFT_LCD_G,         // O [5:0]
  TFT_LCD_B,         // O [5:0]
  TFT_LCD_BLNK  	   // 0
  );

///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////

  // PLB GLOBAL SIGNALS
  input        SYS_plbClk;
  input        SYS_plbReset;

  // PLB REQUEST QUALIFIERS INPUTS
  input         PLB_MnAddrAck;
  input         PLB_MnRearbitrate;
  input  [0:1]  PLB_Mnssize;
  input         PLB_MnBusy;
  input         PLB_MnErr;
  input         PLB_pendReq;
  input  [0:1]  PLB_pendPri;
  input  [0:1]  PLB_reqPri;     
  output        Mn_request;
  output [0:1]  Mn_priority;
  output        Mn_busLock;
  output        Mn_RNW;
  output [0:7]  Mn_BE;
  output [0:3]  Mn_size;        
  output [0:2]  Mn_type;
  output [0:1]  Mn_msize;                
  output        Mn_compress;              
  output        Mn_guarded;    
  output        Mn_ordered;     
  output        Mn_lockErr;      
  output        Mn_abort;      
  output [0:31] Mn_ABus;

  // PLB WRITE DATA BUS
  input         PLB_MnWrDAck;       
  input         PLB_MnWrBTerm;      
  output        Mn_wrBurst;          
  output [0:63] Mn_wrDBus;          

  // PLB READ DATA BUS
  input         PLB_MnRdDAck;     
  input         PLB_MnRdBTerm;      
  input [0:3]   PLB_MnRdWdAddr;
  input [0:63]  PLB_MnRdDBus;        
  output        Mn_rdBurst;      

  // DCR BUS SIGNALS 
  input         SYS_dcrClk;
  input [0:9]   DCR_ABus;
  input [0:31]  DCR_DBusIn;
  input         DCR_Read;
  input         DCR_Write;
  output        DCR_Ack;
  output [0:31] DCR_DBusOut;      

  // TFT SIGNALS
  input         SYS_tftClk;
  output        TFT_LCD_HSYNC;
  output        TFT_LCD_VSYNC;
  output        TFT_LCD_DE;
  output        TFT_LCD_CLK;
  output        TFT_LCD_DPS;
  output [5:0]  TFT_LCD_R;
  output [5:0]  TFT_LCD_G; 
  output [5:0]  TFT_LCD_B;
  output        TFT_LCD_BLNK;
///////////////////////////////////////////////////////////////////////////////
// PARAMETER DECLARATION
///////////////////////////////////////////////////////////////////////////////
  parameter C_DCR_BASEADDR = 10'b00_1000_0000;
  parameter C_DCR_HIGHADDR  = 10'b00_1000_0001;
  parameter C_DEFAULT_TFT_BASE_ADDR = 11'b000_0000_0000;
  parameter C_DPS_INIT = 1'b1;
  parameter C_ON_INIT = 1'b1;
  parameter C_PIXCLK_IS_BUSCLK_DIVBY4  = 1'b1; // when set to one bypasses  SYS_tftClk, and uses a DCM to divide sys clock by 4

///////////////////////////////////////////////////////////////////////////////
// Signal Declaration
///////////////////////////////////////////////////////////////////////////////

  // PLB_IF to RGB_BRAM  
  wire [0:63] PLB_BRAM_data_i;
  wire [0:1]  PLB_BRAM_addr_lsb_i;
  wire        PLB_BRAM_addr_en_i;
  wire        PLB_BRAM_we_i;

  // HSYNC and VSYNC to TFT_IF
  wire        HSYNC_i;
  wire        VSYNC_i;

  // DE GENERATION
  wire        H_DE_i;
  wire        V_DE_i;
  wire        DE_i;

  // RGB_BRAM to TFT_IF
  wire        R0_i;
  wire        R1_i;
  wire        R2_i;
  wire        R3_i;
  wire        R4_i;
  wire        R5_i;
  wire        G0_i;
  wire        G1_i;
  wire        G2_i;
  wire        G3_i;
  wire        G4_i;
  wire        G5_i;
  wire        B0_i;
  wire        B1_i;
  wire        B2_i;
  wire        B3_i;
  wire        B4_i;
  wire        B5_i;

  // VSYNC RESET
  wire         vsync_rst;

  // TFT READ FROM BRAM
  wire         BRAM_TFT_rd;
  wire         BRAM_TFT_oe;

  wire         h_bp_cnt_tc;
  wire         h_bp_cnt_tc2;  
  wire         h_pix_cnt_tc;
  wire         h_pix_cnt_tc2;

  // get line pulse
  reg          get_line;

  // DCR Regs
  wire [0:10]  tft_base_addr_i;
  wire         tft_on_reg;

  wire         v_bp_cnt_tc;
  wire         get_line_start;
  reg          get_line_start_d1;
  reg          get_line_start_d2;
  reg          get_line_start_d3;
  wire         v_l_cnt_tc;

   // Clock wires
  wire         plb_clk;
  wire         tft_clk;
  wire         dcr_clk;
  
  // Reset wires
  wire         tft_rst;  //synthesis syn_keep = 1
  wire         tft_rst1;  //synthesis syn_keep = 1
  wire         tft_rst2;  //synthesis syn_keep = 1
  wire         tft_rst3;  //synthesis syn_keep = 1


  wire buffered_pixel_clock;
  wire CLKDV;
  wire CLK0;