📄 onewire_master.vhd
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-------------------------------------------------------------------------------
-- Title : 1-Wire Master
-- Project :
-------------------------------------------------------------------------------
-- File : onewire_master.vhd
-- Author : Davy Huang <Dai.Huang@Xilinx.com>
-- Company : Xilinx, Inc.
-- Created : 2001/01/31
-- Last Update: 2001-04-18
-- Copyright : (c) Xilinx Inc, 2001
-------------------------------------------------------------------------------
-- Uses : SHReg, BitReg, ByteReg, CRCReg, JCounter
-------------------------------------------------------------------------------
-- Used by : 1-Wire Interface
-------------------------------------------------------------------------------
-- Description: This is the master module to drive the Serial Number Device.
--
-- When communicate with the Serial Number Device, this module
-- works as the master, while the Serial Number Device works as
-- slave. For more information about the Serial Number Device,
-- please refer to the datasheet at:
-- http://www.dalsemi.com/datasheets/pdfs/2401.pdf
--
-- This module has been verified to work with Dallas DS2401
-- Silicon Serial Number Device and DS2430A EEPROM.
--
-- The function provided by this master module include:
-- (1) Send "Reset Pulse" to the Serial Number Device to reset it
-- (2) Detect "Presence Pulse" from the Serial Number Device
-- (3) Control data flow on the bidirectional one-wire bus which
-- connects the Serial Number Device and this master module
-- through one-wire.
-- (4) Read in the 8 bytes of data from the Serial Number Device
-- which include the family code (x01), the serial number
-- (6 bytes), and the CRC value (1 byte)
-- (5) Output the data to the data bus (data) as individual
-- bytes (total 8 bytes) with a data enable signal
-- (data_valid) as the strobe signal.
-- The data bytes follow the sequence:
-- 1. Family Code: (e.g. 0x01 for DS2401 device)
-- 2. Serial Number (Byte 0)
-- 3. Serial Number (Byte 1)
-- 4. Serial Number (Byte 2)
-- 5. Serial Number (Byte 3)
-- 6. Serial Number (Byte 4)
-- 7. Serial Number (Byte 5)
-- 8. CRC Value
-- (6) (optional) Calculate CRC and match it with the CRC value
-- received from the device.
-- (7) Assert CRC OK if [a] all the bytes has been received and
-- sent out to the data bus, and [b] CRC values are
-- matched ([b] is optional).
-- (8) Output the 48 bits serial number at the parallel port
-- (sn_data)
--
-- This module needs an 1MHz (1us period) clock input.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/01/31 1.0 Davy Create the initial design
-- 2001/02/07 1.1 Davy First release
-- 2001/02/08 1.2 Davy Clearify/revise the comments
-- 2001/02/16 1.3 Davy Remove one clock input, optimize design
-- 2001/02/23 1.3 Davy Change name to onewire_master
-- 2001/03/06 1.3 Davy Fix the timing spec err in INIT state
-- 2001/03/15 1.4 Davy Change crc_ok to make it happen earlier, then
-- use crc_ok to lead FSM back to INIT if CRC
-- fails; Add parallel output
-- 2001/04/12 1.5 Davy (1)detect pull-up in RX_PRE_PLS
-- (2)use register instead of latch for din_pp
-- (3)use register instead of latch for crcok_i
-- (4)register the data_valid signal
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- synthesis translate_off
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
-- synthesis translate_on
entity onewire_master is
generic (CheckCRC : boolean := true); -- turn on crc check circuit
-- if it's true; otherwise
-- the crc circuit will be
-- removed to save registers
port (
clk_1MHz : in std_logic; -- clock (typical 1 MHz)
reset : in std_logic; -- reset this circuit,
dq : inout std_logic; -- connect to external
-- one-wire bus.
-- A pullup resistor must be
-- attached to this wire
-- either externally or
-- internally.
data : out std_logic_vector(7 downto 0);
-- data output
-- A byte of data will be
-- available on this data bus
-- when data_valid is
-- asserted.
data_valid: out std_logic; -- data enable strobe,
-- indicates a byte of valid
-- data (20us pulse)
crcok : out std_logic; -- if CheckCRC = true, crcok
-- will give the result of
-- crc verification;
-- otherwise it will be
-- forced to '1' when all the
-- data have been received.
sn_data : out std_logic_vector (47 downto 0)
-- The parallel output of the
-- serial number. If crcok
-- is active, sn_data will be
-- valid 48bits serial number
);
end onewire_master;
architecture rtl of onewire_master is
----------------------------------------------------------------------------
-- Components Declaration
----------------------------------------------------------------------------
component IOBUF -- I/O Bidirectional buffer (T=0 : I=>IO; T=1: IO=>O)
port (
I : in std_logic;
T : in std_logic;
IO : inout std_logic;
O : out std_logic);
end component;
component SHReg -- Parameterisable Shift Register
generic (
width : natural;
AsynReset: boolean;
circular : boolean);
port (
reset : in std_logic; -- synchronous reset
clk : in std_logic;
en : in std_logic;
q : out std_logic_vector((width - 1) downto 0) );
end component;
component BitReg -- Parameterisable Bit Register
generic ( numBits : integer);
port (
clk : in std_logic;
reset : in std_logic; -- asynchronous reset
din : in std_logic;
en : in std_logic_vector((numBits - 1) downto 0);
dout : out std_logic_vector((numBits - 1) downto 0));
end component;
component ByteReg -- Parameterisable Byte Register
generic ( numBytes : integer);
port (
clk : in std_logic;
reset : in std_logic; -- asynchronous reset
din : in std_logic_vector(7 downto 0);
en : in std_logic_vector((numBytes - 1) downto 0);
dout : out std_logic_vector((numBytes * 8 -1) downto 0));
end component;
component JCounter -- Parameterisable Johnson Counter
generic (
width : natural;
AsynReset: boolean); -- use asynchronous reset if true
port (
reset : in std_logic;
clk : in std_logic;
en : in std_logic;
q : out std_logic_vector((width - 1) downto 0));
end component;
component CRCReg -- Parameterisable CRC Shift Register
generic (
width : natural;
feedback1 : natural;
feedback2 : natural);
port (
reset : in std_logic; -- asynchronous reset
clk : in std_logic;
en : in std_logic;
d : in std_logic;
q : out std_logic_vector((width - 1) downto 0));
end component;
----------------------------------------------------------------------------
-- Signals Declaration
----------------------------------------------------------------------------
-- FSM States
type FSMState is (INIT, TX_RST_PLS, RX_PRE_PLS, TX_RD_CMD,
RX_DATA, IDLE);
-- The state variables for the fsm
signal thisState, nextState : FSMState;
-- constant to issue Read ROM Command for DS2401 Serial Number Device
-- which is either 0x33h (for both DS2401 and DS2430A)
-- or 0x0Fh (for DS2401 only).
constant ReadROMCmd : std_logic_vector(7 downto 0) := "00110011";
-- command data bit to transmit
signal tx_cmd_bit : std_logic;
-- internal generated clock (50KHz)
signal clk_50KHz : std_logic;
-- time slot identification signals
signal ts_60_to_80us : std_logic;
signal ts_0_to_10us : std_logic;
signal ts_0_to_1us : std_logic;
signal ts_14_to_15us : std_logic;
-- signals for shift register 1 (SR1)
signal sr1_reset : std_logic;
signal sr1_en : std_logic;
signal sr1_q : std_logic_vector (7 downto 0);
-- signals for shift register 2 (SR2)
signal sr2_reset : std_logic;
signal sr2_en : std_logic;
signal sr2_q : std_logic_vector (7 downto 0);
-- signals for Johnson counter 1(JC1)
signal jc1_reset : std_logic;
signal jc1_q : std_logic_vector (1 downto 0);
-- signals for Johnson counter 2(JC2)
signal jc2_q : std_logic_vector (9 downto 0);
-- signals for the bidirectional data I/O buffer and data path
signal din : std_logic; -- data from one-wire bus
signal dout : std_logic; -- data to one-wire bus
signal d_ctrl : std_logic; -- 0: dout=>dq (write to the bus)
-- 1: din<=dq (read from the bus)
signal din_pp : std_logic; -- data of presence pulse
-- it'll be 0 if presence pulse is detected.
-- signals for bit register (BitReg)
signal bitreg_en : std_logic_vector(7 downto 0); -- enable signal to load
-- one bit of data into the register
-- signals for byte register (ByteReg)
signal bytereg_en : std_logic_vector(5 downto 0); -- enable signal to load
-- one byte of data into the register
-- several data valid signals
signal databit_valid: std_logic;-- databit_valid signal generated from sr1
-- (which identifies states), it's
-- 1us pulse. It indicates
-- the valid data received from the
-- Serial Number Device, excludes
-- the Presence Pulse.
signal databyte_valid: std_logic;
-- valid signal for receiving a byte of
-- the number data from the Serial Number
-- Device.
-- Include: family code, serial number
-- and crc value. It's 1 us pulse.
-- signals for CRC check circuit
signal crcreg_en : std_logic; -- enable one bit data loaded into
-- the CRC Register.
signal crcvalue_i: std_logic_vector (7 downto 0); -- The calculated
-- CRC value from the CRC register
-- some internal signals for internal wiring
signal data_i : std_logic_vector(7 downto 0); -- to data output
signal crcok_i : std_logic; -- to crcok output
-- some signals for wiring
signal vcc : std_logic;
signal gnd : std_logic;
begin
-------------------------------------------------------------------
-- internal wiring
-------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
data <= data_i; -- a byte of number data to outside
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