opb_onewire_v2_1_0.mpd

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BEGIN opb_onewire

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION STYLE = HDL
OPTION HDL = VHDL
OPTION USAGE_LEVEL = BASE_USER
OPTION SIM_MODELS = BEHAVIORAL : STRUCTURAL

IO_INTERFACE IO_IF = onewire_0, IO_TYPE = XIL_ONEWIRE_V1

## Bus Interfaces
BUS_INTERFACE BUS = SOPB, BUS_STD = OPB, BUS_TYPE = SLAVE

## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0xFFFF8000, DT = std_logic_vector, MIN_SIZE = 0x100
PARAMETER C_HIGHADDR = 0xFFFF80FF, DT = std_logic_vector
PARAMETER C_OPB_DWIDTH = 32, DT = integer
PARAMETER C_OPB_AWIDTH = 32, DT = integer
PARAMETER CheckCRC = true, DT = boolean
PARAMETER ADD_PULLUP = true, DT = boolean
PARAMETER CLK_DIV = 15, DT = integer range 0 to 15

## Ports
PORT OPB_Clk = "", DIR = IN, SIGIS = CLK, BUS = SOPB
PORT OPB_Rst = OPB_Rst, DIR = IN, BUS = SOPB
PORT OPB_ABus = OPB_ABus, DIR = IN, VEC = [0:C_OPB_AWIDTH-1], BUS = SOPB
PORT OPB_BE = OPB_BE, DIR = IN, VEC = [0:C_OPB_DWIDTH/8-1], BUS = SOPB
PORT OPB_RNW = OPB_RNW, DIR = IN, BUS = SOPB
PORT OPB_select = OPB_select, DIR = IN, BUS = SOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = IN, BUS = SOPB
PORT OPB_DBus = OPB_DBus, DIR = IN, VEC = [0:C_OPB_DWIDTH-1], BUS = SOPB
PORT OW_DBus = Sl_DBus, DIR = OUT, VEC = [0:C_OPB_DWIDTH-1], BUS = SOPB
PORT OW_errAck = Sl_errAck, DIR = OUT, BUS = SOPB
PORT OW_retry = Sl_retry, DIR = OUT, BUS = SOPB
PORT OW_toutSup = Sl_toutSup, DIR = OUT, BUS = SOPB
PORT OW_xferAck = Sl_xferAck, DIR = OUT, BUS = SOPB
PORT ONEWIRE_DQ = ONEWIRE_DQ, THREE_STATE = FALSE, PERMIT = BASE_USER, IOB_STATE = BUF, DIR = INOUT, DESC = "OneWire Pin", IO_IF = onewire_0, IO_IS = onewire_dq

END