📄 context_rvds.lst
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ARM Macro Assembler Page 1
1 00000000 ;/*
2 00000000 ; * File : context.S
3 00000000 ; * This file is part of RT-Thread RTOS
4 00000000 ; * COPYRIGHT (C) 2006, RT-Thread Development Team
5 00000000 ; *
6 00000000 ; * The license and distribution terms for this file may
be
7 00000000 ; * found in the file LICENSE in this distribution or at
8 00000000 ; * http://www.rt-thread.org/license/LICENSE
9 00000000 ; *
10 00000000 ; * Change Logs:
11 00000000 ; * Date Author Notes
12 00000000 ; * 2009-01-17 Bernard first version
13 00000000 ; */
14 00000000
15 00000000 ;/**
16 00000000 ; * @addtogroup STM32
17 00000000 ; */
18 00000000 ;/*@{*/
19 00000000
20 00000000 E000ED04
NVIC_INT_CTRL
EQU 0xE000ED04 ; interrupt control
state register
21 00000000 E000ED20
NVIC_SYSPRI2
EQU 0xE000ED20 ; system priority r
egister (2)
22 00000000 00FF0000
NVIC_PENDSV_PRI
EQU 0x00FF0000 ; PendSV priority v
alue (lowest)
23 00000000 10000000
NVIC_PENDSVSET
EQU 0x10000000 ; value to trigger
PendSV exception
24 00000000
25 00000000 AREA |.text|, CODE, READONLY, ALIGN=
2
26 00000000 THUMB
27 00000000 REQUIRE8
28 00000000 PRESERVE8
29 00000000
30 00000000 IMPORT rt_thread_switch_interrput_flag
31 00000000 IMPORT rt_interrupt_from_thread
32 00000000 IMPORT rt_interrupt_to_thread
33 00000000
34 00000000 ;/*
35 00000000 ; * rt_base_t rt_hw_interrupt_disable();
36 00000000 ; */
37 00000000 rt_hw_interrupt_disable
PROC
38 00000000 EXPORT rt_hw_interrupt_disable
39 00000000 F3EF 8010 MRS r0, PRIMASK
40 00000004 B672 CPSID I
41 00000006 4770 BX LR
42 00000008 ENDP
43 00000008
ARM Macro Assembler Page 2
44 00000008 ;/*
45 00000008 ; * void rt_hw_interrupt_enable(rt_base_t level);
46 00000008 ; */
47 00000008 rt_hw_interrupt_enable
PROC
48 00000008 EXPORT rt_hw_interrupt_enable
49 00000008 F380 8810 MSR PRIMASK, r0
50 0000000C 4770 BX LR
51 0000000E ENDP
52 0000000E
53 0000000E ;/*
54 0000000E ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32
to);
55 0000000E ; * r0 --> from
56 0000000E ; * r1 --> to
57 0000000E ; */
58 0000000E rt_hw_context_switch
PROC
59 0000000E EXPORT rt_hw_context_switch
60 0000000E 4A21 LDR r2, =rt_interrupt_from_thread
61 00000010 6010 STR r0, [r2]
62 00000012
63 00000012 4A21 LDR r2, =rt_interrupt_to_thread
64 00000014 6011 STR r1, [r2]
65 00000016
66 00000016 4821 LDR r0, =NVIC_INT_CTRL ; trigger th
e PendSV exception
(causes context swi
tch)
67 00000018 F04F 5180 LDR r1, =NVIC_PENDSVSET
68 0000001C 6001 STR r1, [r0]
69 0000001E B662 CPSIE I ; enable interrupts
at processor level
70 00000020 4770 BX LR
71 00000022 ENDP
72 00000022
73 00000022 ; r0 --> swith from thread stack
74 00000022 ; r1 --> swith to thread stack
75 00000022 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from
] stack
76 00000022 rt_hw_pend_sv
PROC
77 00000022 EXPORT rt_hw_pend_sv
78 00000022 481C LDR r0, =rt_interrupt_from_thread
79 00000024 6801 LDR r1, [r0]
80 00000026 B129 CBZ r1, swtich_to_thread ; skip reg
ister save at the f
irst time
81 00000028
82 00000028 F3EF 8109 MRS r1, psp ; get from thread s
tack pointer
83 0000002C E921 0FF0 STMFD r1!, {r4 - r11} ; push r4 - r11
register
84 00000030 6800 LDR r0, [r0]
85 00000032 6001 STR r1, [r0] ; update from threa
d stack pointer
86 00000034
87 00000034 swtich_to_thread
ARM Macro Assembler Page 3
88 00000034 4918 LDR r1, =rt_interrupt_to_thread
89 00000036 6809 LDR r1, [r1]
90 00000038 6809 LDR r1, [r1] ; load thread stack
pointer
91 0000003A
92 0000003A E8B1 0FF0 LDMFD r1!, {r4 - r11} ; pop r4 - r11
register
93 0000003E F381 8809 MSR psp, r1 ; update stack poin
ter
94 00000042
95 00000042 F04E 0E04 ORR lr, lr, #0x04
96 00000046 4770 BX lr
97 00000048 ENDP
98 00000048
99 00000048 ;/*
100 00000048 ; * void rt_hw_context_switch_to(rt_uint32 to);
101 00000048 ; * r0 --> to
102 00000048 ; */
103 00000048 rt_hw_context_switch_to
PROC
104 00000048 EXPORT rt_hw_context_switch_to
105 00000048 4913 LDR r1, =rt_interrupt_to_thread
106 0000004A 6008 STR r0, [r1]
107 0000004C
108 0000004C ; set from thread to 0
109 0000004C 4911 LDR r1, =rt_interrupt_from_thread
110 0000004E F04F 0000 MOV r0, #0x0
111 00000052 6008 STR r0, [r1]
112 00000054
113 00000054 ; set the PendSV exception priority
114 00000054 4812 LDR r0, =NVIC_SYSPRI2
115 00000056 F44F 017F LDR r1, =NVIC_PENDSV_PRI
116 0000005A 6001 STR r1, [r0]
117 0000005C
118 0000005C 480F LDR r0, =NVIC_INT_CTRL ; trigger th
e PendSV exception
(causes context swi
tch)
119 0000005E F04F 5180 LDR r1, =NVIC_PENDSVSET
120 00000062 6001 STR r1, [r0]
121 00000064
122 00000064 B662 CPSIE I ; enable interrupts
at processor level
123 00000066
124 00000066 ; never reach here!
125 00000066 ENDP
126 00000066
127 00000066 ;/*
128 00000066 ; * void rt_hw_context_switch_interrupt(rt_uint32 from,
rt_uint32 to)
129 00000066 ; * {
130 00000066 ; * if (rt_thread_switch_interrput_flag == 1)
131 00000066 ; * {
132 00000066 ; * rt_interrupt_to_thread = to;
133 00000066 ; * }
134 00000066 ; * else
135 00000066 ; * {
136 00000066 ; * rt_thread_switch_interrput_flag = 1;
ARM Macro Assembler Page 4
137 00000066 ; * rt_interrupt_from_thread = from;
138 00000066 ; * rt_interrupt_to_thread = to;
139 00000066 ; * }
140 00000066 ; * }
141 00000066 ; */
142 00000066 rt_hw_context_switch_interrupt
PROC
143 00000066 EXPORT rt_hw_context_switch_interrupt
144 00000066 4A0F LDR r2, =rt_thread_switch_interrput
_flag
145 00000068 6813 LDR r3, [r2]
146 0000006A 2B01 CMP r3, #1
147 0000006C D004 BEQ _reswitch
148 0000006E F04F 0301 MOV r3, #1 ; set rt_thread_swi
tch_interrput_flag
to 1
149 00000072 6013 STR r3, [r2]
150 00000074 4A07 LDR r2, =rt_interrupt_from_thread ;
set rt_interrupt_f
rom_thread
151 00000076 6010 STR r0, [r2]
152 00000078 _reswitch
153 00000078 4A07 LDR r2, =rt_interrupt_to_thread ; s
et rt_interrupt_to_
thread
154 0000007A 6011 STR r1, [r2]
155 0000007C 4770 BX lr
156 0000007E ENDP
157 0000007E
158 0000007E rt_hw_interrupt_thread_switch
PROC
159 0000007E EXPORT rt_hw_interrupt_thread_switch
160 0000007E 4809 LDR r0, =rt_thread_switch_interrput
_flag
161 00000080 6801 LDR r1, [r0]
162 00000082 B131 CBZ r1, _no_switch
163 00000084
164 00000084 ; clear rt_thread_switch_interrput_flag to 0
165 00000084 F04F 0100 MOV r1, #0x00
166 00000088 6001 STR r1, [r0]
167 0000008A
168 0000008A ; trigger context switch
169 0000008A 4804 LDR r0, =NVIC_INT_CTRL ; trigger th
e PendSV exception
(causes context swi
tch)
170 0000008C F04F 5180 LDR r1, =NVIC_PENDSVSET
171 00000090 6001 STR r1, [r0]
172 00000092
173 00000092 _no_switch
174 00000092 4770 BX lr
175 00000094
176 00000094 ENDP
177 00000094
178 00000094 END
00000000
00000000
E000ED04
E000ED20
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