📄 s3c44b0x.h
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/* UMCON */#define S3C44B0X_UMCON_AFC 0x00000010 /* auto flow control */#define S3C44B0X_UMCON_RQST_SEND 0x00000001 /* request to send 1=L(active RTS) 0=H(inactive RTS) *//* UTRSTAT */#define S3C44B0X_UTRSTAT_TSE 0x00000004 /* transmitter shifter empty */#define S3C44B0X_UTRSTAT_TBE 0x00000002 /* transmitt buffer empty */#define S3C44B0X_UTRSTAT_RBDR 0x00000001 /* receive buffer data ready *//* UERSTAT */#define S3C44B0X_UERSTAT_BREAK_DETECT 0x00000008#define S3C44B0X_UERSTAT_FRAME_ERROR 0x00000004#define S3C44B0X_UERSTAT_PARITY_ERROR 0x00000002#define S3C44B0X_UERSTAT_OVERRUN_ERROR 0x00000001/* UFSTAT */#define S3C44B0X_UFSTAT_TX_FIFO_FULL 0x00000200#define S3C44B0X_UFSTAT_RX_FIFO_FULL 0x00000100#define S3C44B0X_UFSTAT_TX_FIFO_COUNT 0x000000F0#define S3C44B0X_UFSTAT_RX_FIFO_COUNT 0x0000000F /***********/ /*** SIO ***/ /***********/#define S3C44B0X_SIOCON 0x01d14000#define S3C44B0X_SIODAT 0x01d14004#define S3C44B0X_SBRDR 0x01d14008#define S3C44B0X_ITVCNT 0x01d1400c#define S3C44B0X_DNCTZ 0x01d14010 /****************************/ /*** IIS (Inter IC Sound) ***/ /****************************/#define S3C44B0X_IISCON 0x01d18000#define S3C44B0X_IISMOD 0x01d18004#define S3C44B0X_IISPSR 0x01d18008#define S3C44B0X_IISFIFCON 0x01d1800c#define S3C44B0X_IISFIF 0x01d18010 /*****************/ /*** I/O ports ***/ /*****************/#define S3C44B0X_PCONA 0x01d20000#define S3C44B0X_PDATA 0x01d20004#define S3C44B0X_PCONB 0x01d20008#define S3C44B0X_PDATB 0x01d2000c#define S3C44B0X_PCONC 0x01d20010#define S3C44B0X_PDATC 0x01d20014#define S3C44B0X_PUPC 0x01d20018#define S3C44B0X_PCOND 0x01d2001c#define S3C44B0X_PDATD 0x01d20020#define S3C44B0X_PUPD 0x01d20024#define S3C44B0X_PCONE 0x01d20028#define S3C44B0X_PDATE 0x01d2002c#define S3C44B0X_PUPE 0x01d20030#define S3C44B0X_PCONF 0x01d20034#define S3C44B0X_PDATF 0x01d20038#define S3C44B0X_PUPF 0x01d2003c#define S3C44B0X_PCONG 0x01d20040#define S3C44B0X_PDATG 0x01d20044#define S3C44B0X_PUPG 0x01d20048#define S3C44B0X_SPUCR 0x01d2004c /***************************/ /*** external interrupts ***/ /***************************/#define S3C44B0X_EXTINT 0x01d20050#define S3C44B0X_EXTINPND 0x01d20054 /**********************/ /*** WATCHDOG TIMER ***/ /**********************/#define S3C44B0X_WTCON 0x01d30000#define S3C44B0X_WTDAT 0x01d30004#define S3C44B0X_WTCNT 0x01d30008 /*********************/ /*** A/D CONVERTER ***/ /*********************/#define S3C44B0X_ADCCON 0x01d40000#define S3C44B0X_ADCPSR 0x01d40004#define S3C44B0X_ADCDAT 0x01d40008 /*****************/ /*** PWM TIMER ***/ /*****************/#define S3C44B0X_TCFG0 0x01d50000 /* prescaler configuration */#define S3C44B0X_TCFG1 0x01d50004 /* MUX-input for PWM and DMA */#define S3C44B0X_TCON 0x01d50008 /* timer control register (start/stop, PWM-out, auto-reload, dead-zone) */#define S3C44B0X_TCNTB0 0x01d5000c /* timer counter "buffer" register (read-write) to update the timer counter */#define S3C44B0X_TCMPB0 0x01d50010 /* timer compare register */#define S3C44B0X_TCNTO0 0x01d50014 /* timer counter "observation" register (real counter value, read-only) */#define S3C44B0X_TCNTB1 0x01d50018#define S3C44B0X_TCMPB1 0x01d5001c#define S3C44B0X_TCNTO1 0x01d50020#define S3C44B0X_TCNTB2 0x01d50024#define S3C44B0X_TCMPB2 0x01d50028#define S3C44B0X_TCNTO2 0x01d5002c#define S3C44B0X_TCNTB3 0x01d50030#define S3C44B0X_TCMPB3 0x01d50034#define S3C44B0X_TCNTO3 0x01d50038#define S3C44B0X_TCNTB4 0x01d5003c#define S3C44B0X_TCMPB4 0x01d50040#define S3C44B0X_TCNTO4 0x01d50044#define S3C44B0X_TCNTB5 0x01d50048#define S3C44B0X_TCNTO5 0x01d5004c/* TCON */#define S3C44B0X_TCON_T5_AUTO 0x04000000 /* automatically reload the timer register (cycle) */#define S3C44B0X_TCON_T5_MAN_UPDATE 0x02000000 /* manualy update the counter (read from TCNTBn) */#define S3C44B0X_TCON_T5_START 0x01000000 /* start the timer (normal modus) if bit not set -> no decrement of counter */#define S3C44B0X_TCON_T4_AUTO 0x00800000#define S3C44B0X_TCON_T4_OUTPUT 0x00400000 /* enable output to the PWM-pin (controlled by TCMPBn and TCNTBn) */#define S3C44B0X_TCON_T4_MAN_UPDATE 0x00200000#define S3C44B0X_TCON_T4_START 0x00100000#define S3C44B0X_TCON_T3_AUTO 0x00080000#define S3C44B0X_TCON_T3_OUTPUT 0x00040000#define S3C44B0X_TCON_T3_MAN_UPDATE 0x00020000#define S3C44B0X_TCON_T3_START 0x00010000#define S3C44B0X_TCON_T2_AUTO 0x00008000#define S3C44B0X_TCON_T2_OUTPUT 0x00004000#define S3C44B0X_TCON_T2_MAN_UPDATE 0x00002000#define S3C44B0X_TCON_T2_START 0x00001000#define S3C44B0X_TCON_T1_AUTO 0x00000800#define S3C44B0X_TCON_T1_OUTPUT 0x00000400#define S3C44B0X_TCON_T1_MAN_UPDATE 0x00000200#define S3C44B0X_TCON_T1_START 0x00000100#define S3C44B0X_TCON_DEAD_ZONE_EN 0x00000010 /* enable the dead zone for PWM-mode */#define S3C44B0X_TCON_T0_AUTO 0x00000008#define S3C44B0X_TCON_T0_OUTPUT 0x00000004#define S3C44B0X_TCON_T0_MAN_UPDATE 0x00000002#define S3C44B0X_TCON_T0_START 0x00000001 /***********/ /*** IIC ***/ /***********/#define S3C44B0X_IICCON 0x01d60000#define S3C44B0X_IICSTAT 0x01d60004#define S3C44B0X_IICADD 0x01d60008#define S3C44B0X_IICDS 0x01d6000c /***********/ /*** RTC ***/ /***********/#define S3C44B0X_RTCCON 0x01d70040#define S3C44B0X_RTCALM 0x01d70050#define S3C44B0X_ALMSEC 0x01d70054#define S3C44B0X_ALMMIN 0x01d70058#define S3C44B0X_ALMHOUR 0x01d7005c#define S3C44B0X_ALMDAY 0x01d70060#define S3C44B0X_ALMMON 0x01d70064#define S3C44B0X_ALMYEAR 0x01d70068#define S3C44B0X_RTCRST 0x01d7006c#define S3C44B0X_BCDSEC 0x01d70070#define S3C44B0X_BCDMIN 0x01d70074#define S3C44B0X_BCDHOUR 0x01d70078#define S3C44B0X_BCDDAY 0x01d7007c#define S3C44B0X_BCDDATE 0x01d70080#define S3C44B0X_BCDMON 0x01d70084#define S3C44B0X_BCDYEAR 0x01d70088#define S3C44B0X_TICINT 0x01d7008c /********************************/ /*** CLOCK & POWER MANAGEMENT ***/ /********************************/#define S3C44B0X_PLLCON 0x01d80000#define S3C44B0X_CLKCON 0x01d80004#define S3C44B0X_CLKSLOW 0x01d80008#define S3C44B0X_LOCKTIME 0x01d8000c#define S3C44B0X_CLKCON_IIS 0x4000#define S3C44B0X_CLKCON_IIC 0x2000#define S3C44B0X_CLKCON_ADC 0x1000#define S3C44B0X_CLKCON_RTC 0x0800#define S3C44B0X_CLKCON_GPIO 0x0400#define S3C44B0X_CLKCON_UART1 0x0200#define S3C44B0X_CLKCON_UART0 0x0100#define S3C44B0X_CLKCON_BDMA 0x0080#define S3C44B0X_CLKCON_LCDC 0x0040#define S3C44B0X_CLKCON_SIO 0x0020#define S3C44B0X_CLKCON_ZDMA 0x0010#define S3C44B0X_CLKCON_PWMTIMER 0x0008#define S3C44B0X_CLKCON_IDLE_BIT 0x0004#define S3C44B0X_CLKCON_SL_IDLE 0x0002#define S3C44B0X_CLKCON_STOP_BIT 0x0001#define S3C44B0X_CLKSLOW_PLL_OFF 0x00000010#define S3C44B0X_CLKSLOW_SLOW_BIT 0x00000008#define S3C44B0X_CLKSLOW_VAL_0 0x00000000#define S3C44B0X_CLKSLOW_VAL_1 0x00000001#define S3C44B0X_CLKSLOW_VAL_2 0x00000002#define S3C44B0X_CLKSLOW_VAL_3 0x00000003 /****************************/ /*** INTERRUPT CONTROLLER ***/ /****************************/#define S3C44B0X_INTCON 0x01e00000#define S3C44B0X_INTPND 0x01e00004#define S3C44B0X_INTMOD 0x01e00008#define S3C44B0X_INTMSK 0x01e0000c#define S3C44B0X_I_PSLV 0x01e00010#define S3C44B0X_I_PMST 0x01e00014#define S3C44B0X_I_CSLV 0x01e00018#define S3C44B0X_I_CMST 0x01e0001c#define S3C44B0X_I_ISPR 0x01e00020#define S3C44B0X_I_ISPC 0x01e00024#define S3C44B0X_F_ISPR 0x01e00038#define S3C44B0X_F_ISPC 0x01e0003c /***********/ /*** DMA ***/ /***********/#define S3C44B0X_ZDCON0 0x01e80000#define S3C44B0X_ZDISRC0 0x01e80004#define S3C44B0X_ZDIDES0 0x01e80008#define S3C44B0X_ZDICNT0 0x01e8000c#define S3C44B0X_ZDCSRC0 0x01e80010#define S3C44B0X_ZDCDES0 0x01e80014#define S3C44B0X_ZDCCNT0 0x01e80018#define S3C44B0X_ZDCON1 0x01e80020#define S3C44B0X_ZDISRC1 0x01e80024#define S3C44B0X_ZDIDES1 0x01e80028#define S3C44B0X_ZDICNT1 0x01e8002c#define S3C44B0X_ZDCSRC1 0x01e80030#define S3C44B0X_ZDCDES1 0x01e80034#define S3C44B0X_ZDCCNT1 0x01e80038#define S3C44B0X_BDCON0 0x01f80000#define S3C44B0X_BDISRC0 0x01f80004#define S3C44B0X_BDIDES0 0x01f80008#define S3C44B0X_BDICNT0 0x01f8000c#define S3C44B0X_BDCSRC0 0x01f80010#define S3C44B0X_BDCDES0 0x01f80014#define S3C44B0X_BDCCNT0 0x01f80018#define S3C44B0X_BDCON1 0x01f80020#define S3C44B0X_BDISRC1 0x01f80024#define S3C44B0X_BDIDES1 0x01f80028#define S3C44B0X_BDICNT1 0x01f8002c#define S3C44B0X_BDCSRC1 0x01f80030#define S3C44B0X_BDCDES1 0x01f80034#define S3C44B0X_BDCCNT1 0x01f80038#define S3C44B0X_ZDCON_STE_RDY 0x00000000#define S3C44B0X_ZDCON_STE_NTC 0x00000040#define S3C44B0X_ZDCON_STE_TC 0x00000080#define S3C44B0X_ZDCON_QDS_EN 0x00000000#define S3C44B0X_ZDCON_QDS_DIS 0x0000000c#define S3C44B0X_ZDCON_CMD_NONE 0x00000000#define S3C44B0X_ZDCON_CMD_START 0x00000001#define S3C44B0X_ZDCON_CMD_PAUSE 0x00000002#define S3C44B0X_ZDCON_CMD_CANCEL 0x00000003/********************* * LCD controller * *********************/#define S3C44B0X_LCD_MEM 0x0c060000#define S3C44B0X_LCDCON1 0x01f00000#define S3C44B0X_LCDCON2 0x01f00004#define S3C44B0X_LCDCON3 0x01f00040#define S3C44B0X_LCDSADDR1 0x01f00008#define S3C44B0X_LCDSADDR2 0x01f0000c#define S3C44B0X_LCDSADDR3 0x01f00010#define S3C44B0X_REDLUT 0x01f00014#define S3C44B0X_GREENLUT 0x01f00018#define S3C44B0X_BLUELUT 0x01f0001c#define S3C44B0X_DP1_2 0x01f00020#define S3C44B0X_DP4_7 0x01f00024#define S3C44B0X_DP3_5 0x01f00028#define S3C44B0X_DP2_3 0x01f0002c#define S3C44B0X_DP5_7 0x01f00030#define S3C44B0X_DP3_4 0x01f00034#define S3C44B0X_DP4_5 0x01f00038#define S3C44B0X_DP6_7 0x01f0003c#define S3C44B0X_DITHMODE 0x01f00044/* LCDCON1 */#define S3C44B0X_LCDCON1_WLH_4 0x00000000#define S3C44B0X_LCDCON1_WLH_8 0x00000400#define S3C44B0X_LCDCON1_WLH_12 0x00000800#define S3C44B0X_LCDCON1_WLH_16 0x00000c00#define S3C44B0X_LCDCON1_WDLY_4 0x00000000#define S3C44B0X_LCDCON1_WDLY_8 0x00000100#define S3C44B0X_LCDCON1_WDLY_12 0x00000200#define S3C44B0X_LCDCON1_WDLY_16 0x00000300#define S3C44B0X_LCDCON1_MMODE 0x00000080#define S3C44B0X_LCDCON1_DISMODE_4D 0x00000000#define S3C44B0X_LCDCON1_DISMODE_4S 0x00000020#define S3C44B0X_LCDCON1_DISMODE_8S 0x00000040#define S3C44B0X_LCDCON1_INVCLK 0x00000010#define S3C44B0X_LCDCON1_INVLINE 0x00000008#define S3C44B0X_LCDCON1_INVFRAME 0x00000004#define S3C44B0X_LCDCON1_INVVD 0x00000002#define S3C44B0X_LCDCON1_ENVID 0x00000001/* LCDCON3 */#define S3C44B0X_LCDCON3_SELFREFRESH 0x00000001/* LCDSADDR1 */#define S3C44B0X_LCDSADDR1_MONO 0x00000000#define S3C44B0X_LCDSADDR1_GRAY_4 0x08000000#define S3C44B0X_LCDSADDR1_GRAY_16 0x10000000#define S3C44B0X_LCDSADDR1_COLOR 0x18000000/* LCDSADDR2 */#define S3C44B0X_LCDSADDR2_BSWP 0x20000000#endif /* _S3C44B0X_H_ */
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